公开(公告)号：US20160365856A1

公开(公告)日：2016-12-15

申请号：US14736213

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Zhengyu DUAN ,  Steven James DILLEN ,  Animesh DATTA

IPC: H03K19/00 ,  H03K3/3562

CPC classification number: H03K19/0013 ,  G01R31/318541 ,  G06F1/04 ,  H03K3/037 ,  H03K3/35625

Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

Abstract translation: MOS器件包括配置有一个锁存器反馈F并被配置为接收锁存器输入I和锁存时钟C的第一锁存器。第一锁存器被配置为输出Q，其中输出Q是CF，IF和IC的函数 并且锁存反馈F是输出Q的函数。第一锁存器可以包括串联堆叠的第一组晶体管，其中第一组晶体管包括至少五个晶体管。 MOS器件还可以包括耦合到第一锁存器的第二锁存器。 第二锁存器可以被配置为扫描模式下的锁存器和功能模式中的脉冲锁存器。 第一锁存器可以作为主锁存器操作，并且第二锁存器可以在扫描模式期间作为从锁存器操作。

公开(公告)号：US20160217227A1

公开(公告)日：2016-07-28

申请号：US14603281

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Peeyush Kumar PARKAR ,  Vijayalakshmi RANGANNA ,  Animesh DATTA ,  Sachin BAPAT

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: At least one critical path is determined of a plurality of paths in a network of logic elements. In addition, a plurality of original cells is determined in a critical path of the at least one critical path. Each intermediate output of the plurality of original cells is unconnected to any input external to the plurality of original cells. The plurality of original cells performs a particular logic function. Furthermore, the plurality of original cells are replaced with at least one replacement cell that performs the particular logic function. A number of cells of the at least one replacement cell is less than a number of cells of the plurality of original cells. The plurality of paths may be between a first memory stage and a second memory stage, and each of the at least one critical path may have a delay greater than a delay threshold.

Abstract translation: 确定逻辑元件网络中的多个路径的至少一个关键路径。 另外，在至少一个关键路径的关键路径中确定多个原始小区。 多个原始单元的每个中间输出与多个原始单元外部的任何输入未连接。 多个原始单元执行特定的逻辑功能。 此外，多个原始单元被替换为执行特定逻辑功能的至少一个替换单元。 所述至少一个替换单元的多个单元小于所述多个原始单元的多个单元。 多个路径可以在第一存储器级和第二存储器级之间，并且至少一个关键路径中的每一个可以具有大于延迟阈值的延迟。

公开(公告)号：US20160211846A1

公开(公告)日：2016-07-21

申请号：US14598182

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Steven James DILLEN ,  Animesh DATTA

IPC: H03K19/00 ,  H03K17/687

CPC classification number: H03K19/0016 ,  H03K17/6872

Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

Abstract translation: CGC包括使能模块和锁存模块。 启用模块具有使能模块输入和使能模块输出。 锁存模块具有锁存模块输入和锁存模块输出。 锁存模块输入包括用于接收时钟的锁存模块时钟输入和用于接收使能模块输出的锁存模块使能输入。 锁存模块使能输入耦合到使能模块输出。 锁存模块被配置为通过基于使能模块输入的锁存模块输出来启用和禁用时钟。 锁存模块包括作为锁存模块输出的内部使能节点。 锁存模块被配置为使内部使能节点根据使能模块输出和ĒC的功能从低电平转换到高电平，其中E是内部使能节点，C是时钟。

公开(公告)号：US20150221639A1

公开(公告)日：2015-08-06

申请号：US14169592

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Satyanarayana SAHU ,  Divya GANGADHARAN ,  Chih-lung KAO ,  Renukprasad Shreedhar HIREMATH ,  Animesh DATTA ,  Qi YE

IPC: H01L27/088 ,  G06F17/50 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/088 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0653 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract translation: 包括标准单元的CMOS器件包括在第一和第二晶体管之间具有栅极的第一和第二晶体管。 一个有源区域在第一和第二晶体管之间以及栅极之下延伸。 在第一种配置中，当栅极侧面的第一和第二晶体管的漏极/源极具有相同的信号时，漏极/源极连接在一起并连接到栅极。 在第二配置中，当栅极侧的第一晶体管的源极连接到源极电压，并且在栅极的另一侧上的第二晶体管的漏极/源极传送信号时，第一晶体管的源极 连接到门。 在第三种配置中，当栅极侧面的第一和第二晶体管的源极连接到源极电压时，栅极浮动。

公开(公告)号：US20150054568A1

公开(公告)日：2015-02-26

申请号：US13975185

申请日：2013-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract translation: 具有多个PMOS晶体管的CMOS器件，每个具有PMOS漏极和多个NMOS晶体管，每个具有NMOS漏极包括在长度方向上延伸的互连级上的第一互连，以将PMOS漏极连接在一起。 互连级上的第二互连在长度方向上延伸以将NMOS漏极连接在一起。 在至少一个附加互连级上的一组互连将第一互连和第二互连耦合在一起。 互连层上的第三互连件垂直于长度方向延伸，并且从互连组中偏移以将第一互连和第二互连连接在一起。