公开(公告)号：US20170068458A1

公开(公告)日：2017-03-09

申请号：US14844443

申请日：2015-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Jung Pill Kim

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0685

Abstract: Hardware-accelerated storage compression is disclosed. In one aspect, prior to writing an uncompressed data block to a storage device, a hardware compression accelerator provided in a storage controller compresses the uncompressed data block into a compressed data block and allocates the compressed data block to a physical data block in the storage device. The hardware compression accelerator then generates a modified logical block address (LBA) to link the uncompressed data block to the compressed data block. In another aspect, the hardware compression accelerator locates a compressed data block based on a corresponding modified LBA and decompresses the compressed data block into an uncompressed data block. By performing hardware-accelerated storage compression in the storage controller, it is possible to reduce processing overhead associated with conventional software-based compression systems and improve compression control over conventional storage-device-driven compression systems.

Abstract translation: 公开了硬件加速存储压缩。 一方面，在将未压缩数据块写入存储装置之前，设置在存储控制器中的硬件压缩加速器将未压缩数据块压缩为压缩数据块，并将压缩数据块分配给存储装置中的物理数据块 。 硬件压缩加速器然后生成修改的逻辑块地址（LBA），以将未压缩的数据块链接到压缩数据块。 在另一方面，硬件压缩加速器基于对应的修改的LBA定位压缩数据块，并将压缩数据块解压缩为未压缩的数据块。 通过在存储控制器中执行硬件加速存储压缩，可以减少与传统的基于软件的压缩系统相关联的处理开销，并且改进对传统的存储设备驱动的压缩系统的压缩控制。

公开(公告)号：US09514082B2

公开(公告)日：2016-12-06

申请号：US14295653

申请日：2014-06-04

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Henry Laurel Sanchez ,  Hung Quoc Vuong ,  Amit Gil

IPC: G06F12/02 ,  G06F13/40 ,  G06F13/42 ,  G11C16/14 ,  G11C16/34 ,  G11C16/20

Abstract: Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time.

公开(公告)号：US20160070656A1

公开(公告)日：2016-03-10

申请号：US14838995

申请日：2015-08-28

Applicant: QUALCOMM Incorporated

Inventor： Benish Babu ,  Yoni Kahana ,  Hyunsuk Shin

IPC: G06F12/14 ,  G06F3/06

CPC classification number: G06F12/1433 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0685 ,  G06F8/654 ,  G06F12/14 ,  G06F12/1441 ,  G06F21/572 ,  G06F2212/1052 ,  G06F2212/177 ,  H04W12/0023 ,  H04W12/1208

Abstract: Write protection management systems are disclosed. In this regard, in one exemplary aspect, a security control system is provided to authorize and write a specified number of data blocks to a write-protected region in a storage device. In another exemplary aspect, a write control system is provided to keep track of data blocks written to the write-protected region. The write control system automatically re-enables write protection on the write-protected region after the specified number of data blocks has been written to the write-protected region. By automatically protecting the write-protected region after writing the specified number of data blocks, it is possible to prevent unauthorized attempts to write to the write-protected region, thus ensuring data security and integrity in the write-protected region.

Abstract translation: 公开了写保护管理系统。 在这方面，在一个示例性方面，提供了一种安全控制系统，用于将指定数量的数据块授权并写入存储设备中的写保护区域。 在另一示例性方面，提供写入控制系统以跟踪写入写保护区域的数据块。 在将指定数量的数据块写入写保护区域之后，写控制系统自动重新启用写保护区上的写保护。 通过在写入指定数量的数据块之后自动保护写保护区域，可以防止未经授权的尝试写入写保护区域，从而确保写保护区域中的数据安全性和完整性。

公开(公告)号：US10802736B2

公开(公告)日：2020-10-13

申请号：US16030841

申请日：2018-07-09

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Todd Christopher Reynolds ,  Hung Vuong

IPC: G06F3/06 ,  G11C5/14 ,  G06F1/3234 ,  G11C16/30 ,  G06F13/16

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

公开(公告)号：US10115444B1

公开(公告)日：2018-10-30

申请号：US15672992

申请日：2017-08-09

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Jung Pill Kim ,  Sungryul Kim

IPC: G11C11/16 ,  G06F13/42 ,  G06F11/10 ,  H03M13/29 ,  G11C29/50 ,  G11C29/04 ,  G11C13/00

Abstract: Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.

公开(公告)号：US11029856B2

公开(公告)日：2021-06-08

申请号：US16287393

申请日：2019-02-27

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Hung Vuong

IPC: G06F3/06 ,  G06F11/30 ,  G06F12/02 ,  G11C16/06

Abstract: Methods and apparatuses to fragment data in a flash memory device are presented. The apparatus includes a host configured to request a flash memory device, via a memory bus, to fragment data stored in the flash memory device in response to a determination of a data fragmentation status of the flash memory device exceeding a threshold. The method includes determining a data fragmentation status of the flash memory device exceeding a threshold and requesting, by a host, the flash memory device to fragment data stored in the flash memory device in response to the determining the data fragmentation status exceeding the threshold.

公开(公告)号：US10510382B2

公开(公告)日：2019-12-17

申请号：US15782833

申请日：2017-10-12

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  David Teb ,  Hung Vuong ,  Venkatakrishnan Gopalakrishnan

IPC: G11C7/10 ,  G06F13/42 ,  G06F13/10 ,  G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: In conventional systems with a plurality of UFS devices daisy-chained to a UFS host, a UFS device driver must be able to differentiate among the links, and send either link control messages or data/management (D/M) messages to a UFS host controller. This can make force the UFS device driver to be complicated and error prone. To address this issue, a host controller can provide a uniform view of a plurality of daisy-chained devices to a device driver of a host. For example, the host controller can be such that from the perspective of the device driver, each device can appear to be a point-to-point connected device. This can allow the device driver to use a same set of link control messages to control the links. In this way, the device driver can be simplified and thus less error prone.

公开(公告)号：US10444999B2

公开(公告)日：2019-10-15

申请号：US15292675

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  David Teb ,  Hung Vuong

IPC: G06F3/06 ,  G06F13/40

Abstract: Systems and method are directed to a Universal Flash Storage (UFS) host capable of interfacing one or more UFS devices. The UFS host includes a plurality of mobile-physical-layers (M-PHYs) for supporting one or more lanes of traffic between the UFS host and the one or more UFS devices. A Reference M-PHY MODULE Interface (RMMI) router is coupled between a Unified Protocol link layer (Unipro) and the plurality of M-PHYs. The RMMI router is configurable in a transparent mode to pass traffic, without routing, between the UFS host and a 2-lane embedded UFS device through the two M-PHYs. The RMMI router is configurable in a routing mode, to route traffic to a first M-PHY interfacing a 1-lane embedded UFS device or to a second M-PHY interfacing a 1-lane removable UFS card. The RMMI router is configurable based on metal strap or read only memory (ROM) setting.

公开(公告)号：US10185515B2

公开(公告)日：2019-01-22

申请号：US14016717

申请日：2013-09-03

Applicant: QUALCOMM Incorporated

Inventor： Hyunsuk Shin ,  Jung Pill Kim ,  Dexter Tamio Chun ,  Jungwon Suh

IPC: G06F3/06 ,  G06F13/16

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

公开(公告)号：US09575884B2

公开(公告)日：2017-02-21

申请号：US13892433

申请日：2013-05-13

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Anand Srinivasan ,  Hyunsuk Shin ,  Steven Haehnichen

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

Abstract translation: 方面包括用于增加闪存设备的闪存转换层（FTL）的性能的系统和方法。 存储在闪存设备上的FTL表的副本可以被复制到主机设备的存储器。 FTL表的副本可以由闪存设备直接访问，以在主机设备提供的逻辑地址之间转换用于从闪存设备的闪速存储器读取/写入操作的闪存以及闪存的相应物理地址 记忆。 闪存设备被授予对存储FTL表的副本的主机设备的存储器的一部分的直接存储器访问。 闪存设备总线将连接闪存设备的通信总线连接到主机设备的存储器。