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公开(公告)号：US11907555B2
公开(公告)日：2024-02-20
申请号：US17989838
申请日：2022-11-18
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
CPC classification number: G06F3/0635 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1678 , Y02D10/00
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US11755521B2
公开(公告)日：2023-09-12
申请号：US17809688
申请日：2022-06-29
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
CPC classification number: G06F13/4022 , G06F12/00 , G06F13/00 , G06F13/1673 , G06F13/1694
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US11520508B2
公开(公告)日：2022-12-06
申请号：US16880244
申请日：2020-05-21
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US20200348870A1
公开(公告)日：2020-11-05
申请号：US16880244
申请日：2020-05-21
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US09804931B2
公开(公告)日：2017-10-31
申请号：US14568768
申请日：2014-12-12
Applicant: Rambus Inc.
Inventor： Steven Woo , David Secker , Ravindranath Kollipara
CPC classification number: G06F11/1456 , G06F1/12 , G06F11/1666 , G06F11/20 , G06F11/2058 , G06F13/4234 , G06F2201/84
Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.
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Patent Agency Ranking
公开(公告)号：US09747230B2
公开(公告)日：2017-08-29
申请号：US14408955
申请日：2013-10-14
Applicant: Rambus Inc.
Inventor： Minghui Han , Amir Amirkhany , Ravindranath Kollipara , Ralf Michael Schmitt
CPC classification number: G06F13/28 , G06F3/0611 , G06F3/0635 , G06F3/0683 , G11C5/04 , G11C5/063 , G11C7/1084
Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.
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公开(公告)号：US09489323B2
公开(公告)日：2016-11-08
申请号：US14182986
申请日：2014-02-18
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
CPC classification number: G06F13/4022 , G06F12/00 , G06F13/00 , G06F13/1673 , G06F13/1694
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
Abstract translation: 存储器模块包括数据接口，该数据接口包括多个数据线和耦合在数据接口和到一个或多个存储器的数据路径之间的多个可配置开关。 可以通过启用或禁用可配置开关的不同子集来配置内存模块的有效宽度。 可配置开关可以由手动开关，存储器模块上的缓冲器，外部存储器控制器或存储器模块上的存储器来控制。
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公开(公告)号：US09373384B2
公开(公告)日：2016-06-21
申请号：US13845503
申请日：2013-03-18
Applicant: Rambus Inc.
Inventor： Ravindranath Kollipara , Lei Luo , Ian Shaeffer
IPC: H03K19/003 , G11C11/401 , G11C5/04 , G11C7/10
CPC classification number: G11C11/401 , G11C5/04 , G11C7/1057 , G11C7/1084
Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.
Abstract translation: 实施例涉及具有可编程输入电容的集成电路器件。 例如，存储器件的可编程寄存器可以存储代表控制引脚的输入电容值的调整值。 一个实施例旨在通过允许较轻负载的引脚的可编程性来控制同步存储器系统的偏斜，以便增加它们的负载以匹配负载较重的引脚。 通过将较轻负载的引脚匹配到负载较重的引脚，系统表现出改进的控制和地址引脚的传播延迟同步。 此外，实施例提供了根据设备上多少等级来改变负载的能力。
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公开(公告)号：US09298228B1
公开(公告)日：2016-03-29
申请号：US14810410
申请日：2015-07-27
Applicant: Rambus Inc.
Inventor： Abhijit M. Abhyankar , Ravindranath Kollipara , Thomas J. Giovannini , Ming Li , David A. Secker , Arun Vaidyanath , Donald R. Mullen , Adrian F. Torres
CPC classification number: G06F1/185
Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.
Abstract translation: 具有存储器提升子子系统的计算系统。 计算系统包括具有存储器模块连接器的主板和插入到第一存储器模块连接器中的转接卡。 第一个夹层卡连接到转接卡。 第一夹层卡包括用于第一存储器模块的第一夹层存储器模块连接器和用于第二存储器模块的第二夹层存储器模块连接器。 存储通道经由主板，第一转接卡和第一夹层卡将存储器控制器电连接到第一夹层存储器模块连接器和第二夹层模块连接器。 存储器通道可以被分成连接到第一夹层存储器模块连接器的第一数据子通道和连接到第二夹层存储器模块连接器的第二数据子通道。
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公开(公告)号：US20240020258A1
公开(公告)日：2024-01-18
申请号：US18355660
申请日：2023-07-20
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
CPC classification number: G06F13/4022 , G06F13/1673 , G06F12/00 , G06F13/00 , G06F13/1694
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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