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    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER
    12.
    发明申请
    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 有权
    减少时钟抖动的方法和电路

    公开(公告)号：US20150036775A1

    公开(公告)日：2015-02-05

    申请号：US14518061

    申请日：2014-10-20

    Applicant: Rambus Inc.

    Inventor： Jared Zerbe ,  Teva Stone ,  Jihong Ren

    IPC: H04L7/02

    CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

    Data Transmission Using Delayed Timing Signals
    13.
    发明申请
    Data Transmission Using Delayed Timing Signals 有权
    使用延迟定时信号进行数据传输

    公开(公告)号：US20140293710A1

    公开(公告)日：2014-10-02

    申请号：US14351955

    申请日：2012-10-26

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G11C7/22

    CPC classification number: H03K5/13 ,  G06F13/00 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Abstract translation: 集成电路包括延迟电路和第一和第二接口电路。 延迟电路将第一定时信号延迟内部延迟以产生内部定时信号。 第一接口电路响应于内部定时信号将数据传送到外部设备。 第二接口电路发送用于捕获外部设备中的数据的外部定时信号。 外部延迟被添加到外部设备中的外部定时信号以产生延迟的外部定时信号。 延迟电路基于延迟的外部定时信号和由第一接口电路发送的校准信号之间的比较来设置内部延迟。

    Data Transmission Using Delayed Timing Signals
    14.
    发明申请
    Data Transmission Using Delayed Timing Signals 有权

    公开(公告)号：US20230073567A1

    公开(公告)日：2023-03-09

    申请号：US17883345

    申请日：2022-08-08

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER
    15.
    发明申请
    METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 有权
    减少时钟抖动的方法和电路

    公开(公告)号：US20140152357A1

    公开(公告)日：2014-06-05

    申请号：US13878351

    申请日：2011-10-03

    Applicant: RAMBUS INC.

    Inventor： Jared Zerbe ,  Teva Stone ,  Jihong Ren

    IPC: H03L7/00

    CPC classification number: H04L7/02 ,  H03K5/1252 ,  H03L7/00

    Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

    Abstract translation: 通信系统包括时钟转发路径中的连续时间线性均衡器。 可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。 降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

    Data transmission using delayed timing signals
    17.
    发明授权
    Data transmission using delayed timing signals 有权

    公开(公告)号：US10700671B2

    公开(公告)日：2020-06-30

    申请号：US15824892

    申请日：2017-11-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian S. Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  G06F13/42 ,  G06F13/00 ,  G11C7/04

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Method And Apparatus For Evaluating And Optimizing A Signaling System
    19.
    发明申请
    Method And Apparatus For Evaluating And Optimizing A Signaling System 有权
    用于评估和优化信号系统的方法和装置

    公开(公告)号：US20150078426A1

    公开(公告)日：2015-03-19

    申请号：US14318557

    申请日：2014-06-27

    Applicant: Rambus Inc.

    Inventor： Jared Zerbe ,  Pak Shing Chau ,  William Franklin Stonecypher

    IPC: H04L1/24 ,  H04L25/03

    CPC classification number: H04L1/244 ,  G01R31/31703 ,  G01R31/31713 ,  G01R31/31716 ,  G01R31/31717 ,  G01R31/3183 ,  G01R31/31855 ,  G01R31/318577 ,  G01R31/3187 ,  G06F11/221 ,  G06F11/26 ,  G06F13/423 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/40 ,  H04B1/04 ,  H04B1/16 ,  H04B3/32 ,  H04B17/0085 ,  H04L1/0001 ,  H04L1/242 ,  H04L1/243 ,  H04L5/1438 ,  H04L25/03885

    Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

    Abstract translation: 描述了用于评估和优化信令系统的方法和装置。 在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。 在接收电路中产生类似的信息模式并用作参考。 接收电路比较图案。 模式之间的任何差异是可观察的。 在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。 本公开的实施例可以用各种类型的信令系统来实施，包括具有单端信号和具有差分信号的信令系统。 本公开的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统以及同时在单个导体上传送多个信息位的系统。

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