公开(公告)号：US12130772B2

公开(公告)日：2024-10-29

申请号：US17971964

申请日：2022-10-24

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Evan Lawrence Erickson

IPC: G06F15/78 ,  G06F21/72

CPC classification number: G06F15/7807 ,  G06F21/72

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.

公开(公告)号：US12001697B2

公开(公告)日：2024-06-04

申请号：US17503058

申请日：2021-10-15

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven C. Woo ,  Michael Raymond Miller

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0673

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

公开(公告)号：US12001283B2

公开(公告)日：2024-06-04

申请号：US18130810

申请日：2023-04-04

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Stephen Magee ,  John Eric Linstadt

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US20240086325A1

公开(公告)日：2024-03-14

申请号：US18242344

申请日：2023-09-05

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Michael Raymond Miller ,  Steven C. Woo

IPC: G06F12/0815 ,  G06F12/123

CPC classification number: G06F12/0815 ,  G06F12/123 ,  G06F2212/305

Abstract: A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit/miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit/miss determination for cache-line read/write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.

公开(公告)号：US11842762B2

公开(公告)日：2023-12-12

申请号：US17439215

申请日：2020-03-16

Applicant: RAMBUS INC.

Inventor： Frederick Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/2245

Abstract: Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

公开(公告)号：US20220137843A1

公开(公告)日：2022-05-05

申请号：US17503058

申请日：2021-10-15

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven C. Woo ,  Michael Raymond Miller

IPC: G06F3/06

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

公开(公告)号：US20250036304A1

公开(公告)日：2025-01-30

申请号：US18786883

申请日：2024-07-29

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dongyun Lee

IPC: G06F3/06

Abstract: A control component implements pipelined data processing operations in either of two timing domains bridged by a domain-crossing circuit according to one or more configuration signals that indicate relative clock frequencies of the two domain and/or otherwise indicate which of the two timing domains will complete the data processing operations with lowest latency.

公开(公告)号：US20240311334A1

公开(公告)日：2024-09-19

申请号：US18624877

申请日：2024-04-02

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Michael Raymond Miller

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

公开(公告)号：US12072807B2

公开(公告)日：2024-08-27

申请号：US17058492

申请日：2019-05-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/00 ,  G06F12/0864

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US11960438B2

公开(公告)日：2024-04-16

申请号：US17410786

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Michael Raymond Miller

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.