公开(公告)号：US20250015138A1

公开(公告)日：2025-01-09

申请号：US18892925

申请日：2024-09-23

Applicant: Renesas Electronics Corporation

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20240387648A1

公开(公告)日：2024-11-21

申请号：US18616917

申请日：2024-03-26

Applicant: Renesas Electronics Corporation

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Tomoya NISHIMURA

IPC: H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423

Abstract: Performance of a semiconductor device is improved. In a semiconductor substrate (SUB), a trench TR1 and a trench TR2 are formed so as to reach a predetermined depth from an upper surface (TS) of the semiconductor substrate (SUB). A field-plate electrode (FP) is formed at a lower portion of the trench TR1, and a gate-electrode GE1 is formed at an upper portion of the trench TR1. A gate electrode GE2 is formed inside the trench TR2. The depth of the trench TR1 is deeper than the depth of the trench TR2. The trench TR1 is surrounded by the trench TR2 in plan view.

公开(公告)号：US20240113218A1

公开(公告)日：2024-04-04

申请号：US18353250

申请日：2023-07-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoya NISHIMURA ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734

Abstract: A first trench extending in a Y direction is formed in each of a semiconductor substrate located in a cell region and the semiconductor substrate located in an outer peripheral region. A second trench is formed in the semiconductor substrate in the outer peripheral region so as to surround the cell region in a plan view. A p-type body region is formed in the semiconductor substrate in each region. A plurality of p-type floating regions is formed in the semiconductor substrate in the outer peripheral region. A field plate electrode is formed at a lower portion of each of the first trench and the second trench. A gate electrode is formed at an upper portion of the first trench located in the cell region. A floating gate electrode is formed at an upper portion of each of the first trench located in the outer peripheral region and the second trench.

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210159331A1

公开(公告)日：2021-05-27

申请号：US17095241

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Satoru TOKUDA ,  Ryuuji UMEMOTO ,  Katsumi EIKYU ,  Hiroshi YANAGIGAWA

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

公开(公告)号：US20150130009A1

公开(公告)日：2015-05-14

申请号：US14528724

申请日：2014-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi EIKYU ,  Atsushi SAKAI ,  Hiroyuki ARIE

IPC: H01L27/146 ,  H01L31/18 ,  H01L31/028

CPC classification number: H01L27/14645 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804

Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.

Abstract translation: 为了提供具有高灵敏度的光电转换元件的半导体器件，引起较少的起霜，并且能够提供高可靠性的图像。 半导体器件具有半导体衬底，第一p型外延层，第二p型外延层和第一光电转换元件。 第一p型外延层形成在半导体衬底的主表面上。 形成第二p型外延层以覆盖第一p型外延层的上表面。 第一光电转换元件形成在第二p型外延层中。 第一和第二p型外延层各自由硅制成，并且第一p型外延层的p型杂质浓度高于第二p型外延层的p型杂质浓度。

公开(公告)号：US20230369414A1

公开(公告)日：2023-11-16

申请号：US18358474

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/66734 ,  H01L29/7813

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20230112550A1

公开(公告)日：2023-04-13

申请号：US17886073

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta NABUCHI ,  Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Atsushi SAKAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/266

Abstract: A semiconductor device and a method of manufacturing the same capable of ensuring a sufficient breakdown voltage near a terminal end portion of a cell portion are provided. The cell portion includes a first cell column region and a second cell column region adjacent to each other, and a first cell trench gate and a second cell trench gate arranged between the first cell column region and the second cell column region. An outer peripheral portion includes an outer peripheral trench gate connected to an end portion of each of the first cell trench gate and the second cell trench gate, and a first outer peripheral column region arranged on the cell portion side with respect to the outer peripheral trench gate and extended across the first cell trench gate and the second cell trench gate in plan view.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20190198663A1

公开(公告)日：2019-06-27

申请号：US16192480

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.