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    SEMICONDUCTOR DEVICE
    11.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180019748A1

    公开(公告)日：2018-01-18

    申请号：US15596802

    申请日：2017-05-16

    Applicant: Renesas Electronics Corporation

    Inventor： Digh HISAMOTO

    IPC: H03K17/30 ,  G11C11/419 ,  H01L27/088 ,  H03K17/16

    CPC classification number: H03K17/302 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L27/0886 ,  H03K17/161 ,  H03K2217/0036

    Abstract: A semiconductor device includes a driver circuit having a plurality of FinFETs, a memory cell having a plurality of FinFETs and supplied with a first output signal from the driver circuit through each of word lines, a first power supply wiring supplied with a first power supply potential, a second power supply wiring supplied with a second power supply potential, and a ground potential setting circuit which is coupled to the first power supply wiring, the second power supply wiring, and the driver circuit and which selects the first power supply potential or the second power supply potential and supplies the same to the driver circuit as an operating potential. An N-type FinFET of the FinFETs included in the driver circuit is supplied with the first power supply potential or the second power supply potential selected by the ground potential setting circuit.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    12.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150270279A1

    公开(公告)日：2015-09-24

    申请号：US14664493

    申请日：2015-03-20

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi ARIGANE ,  Digh HISAMOTO ,  Daisuke OKADA

    IPC: H01L27/115 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762 ,  H01L29/423 ,  H01L21/306 ,  H01L21/28 ,  H01L29/06 ,  H01L29/792 ,  H01L29/51

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

    Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.

    Abstract translation: 存储栅极由包括由第二绝缘膜和第一存储栅电极构成的第二栅绝缘膜的第一存储栅形成，以及包括由第三绝缘膜和第二存储器构成的第三栅绝缘膜的第二存储栅 栅电极。 此外，第二存储栅电极的下表面位于比第一存储栅电极的下表面更低的电平。 结果，在擦除操作期间，电场集中在位于更靠近选择栅极和半导体衬底的位于第一存储栅电极的角部上，并且位于位于第二存储栅电极的拐角部分 更靠近第一存储器栅极和半导体衬底。 这允许容易地将孔注入到每个第二和第三绝缘膜中。

    Semiconductor Device
    13.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20150137215A1

    公开(公告)日：2015-05-21

    申请号：US14609659

    申请日：2015-01-30

    Applicant: Renesas Electronics Corporation

    Inventor： Tsutomu OKAZAKI ,  Daisuke OKADA ,  Kyoya NITTA ,  Toshihiro TANAKA ,  Akira KATO ,  Toshikazu MATSUI ,  Yasushi ISHII ,  Digh HISAMOTO ,  Kan YASUI

    IPC: H01L27/115

    CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

    Abstract translation: 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200035693A1

    公开(公告)日：2020-01-30

    申请号：US16460476

    申请日：2019-07-02

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA

    IPC: H01L27/1158 ,  H01L27/11568 ,  H01L27/11565

    Abstract: In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.

    SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF
    20.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20140327066A1

    公开(公告)日：2014-11-06

    申请号：US14335401

    申请日：2014-07-18

    Applicant: Renesas Electronics Corporation

    Inventor： Itaru YANAGI ,  Toshiyuki MINE ,  Hirotaka HAMAMURA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO

    IPC: H01L29/792

    CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/513

    Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p|-type polysilicon film with a high impurity concentration deposited thereon.

    Abstract translation: 在通过将电子和空穴注入到用作电荷累积层的氮化硅膜中来改变总电荷量进行写/擦除的非易失性存储器中，为了实现从栅极的空穴注入的高效率 电极，存储单元的栅电极包括由具有不同杂质浓度的多个多晶硅膜制成的层压结构，例如包括具有低杂质浓度的p型多晶硅膜和具有较低杂质浓度的双层结构的双层结构 沉积有高杂质浓度的多晶硅膜。

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