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公开(公告)号：US20140241051A1
公开(公告)日：2014-08-28
申请号：US14269173
申请日：2014-05-04
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Satoru HANZAWA , Fumihiko NITTA , Nozomu MATSUZAKI , Toshihiro TANAKA
CPC classification number: G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
Abstract translation: 在包括由可变电阻器使用存储元件的存储器单元和选择晶体管形成的存储单元阵列的半导体器件中，缓冲单元布置在读出放大器和存储单元阵列之间以及字驱动器和存储单元阵列之间 。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。
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公开(公告)号：US20180047452A1
公开(公告)日：2018-02-15
申请号：US15796193
申请日：2017-10-27
Applicant: Renesas Electronics Corporation
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26 , G11C5/02 , H01L29/792
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20190386013A1
公开(公告)日：2019-12-19
申请号：US16552524
申请日：2019-08-27
Applicant: Renesas Electronics Corporation
Inventor： Tsutomu OKAZAKI , Akira KATO , Kan YASUI , Kyoya NITTA , Digh HISAMOTO , Yasushi ISHII , Daisuke OKADA , Toshihiro TANAKA , Toshikazu MATSUI
IPC: H01L27/1157 , H01L29/51 , H01L29/06 , H01L29/792 , H01L29/66 , H01L29/423 , H01L27/11568 , H01L27/115 , H01L27/02 , G11C16/04 , H01L21/28 , H01L27/105
Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
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公开(公告)号：US20190096896A1
公开(公告)日：2019-03-28
申请号：US16200756
申请日：2018-11-27
Applicant: Renesas Electronics Corporation
Inventor： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATO , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
IPC: H01L27/1157 , H01L27/105 , H01L29/423 , H01L29/51 , H01L29/06 , H01L27/115 , H01L27/02 , H01L29/792 , H01L21/28 , H01L29/66 , H01L27/11568 , G11C16/04
CPC classification number: H01L27/1157 , G11C16/0425 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/40117 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
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公开(公告)号：US20180374542A1
公开(公告)日：2018-12-27
申请号：US16116893
申请日：2018-08-29
Applicant: Renesas Electronics Corporation
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26 , G11C16/30 , G11C16/04 , G11C8/08 , G11C5/02 , H01L21/28 , G11C16/24 , H01L29/792 , H01L29/788 , H01L29/66 , H01L29/423 , H01L27/11546 , H01L27/11526 , H01L27/11521 , H01L27/115 , H01L27/105 , G11C16/08
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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Patent Agency Ranking
公开(公告)号：US20130235668A1
公开(公告)日：2013-09-12
申请号：US13867055
申请日：2013-04-20
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20170229469A1
公开(公告)日：2017-08-10
申请号：US15581576
申请日：2017-04-28
Applicant: Renesas Electronics Corporation
Inventor： Tsutomu OKAZAKI , Daisuke OKADA , Kyoya NITTA , Toshihiro TANAKA , Akira KATO , Toshikazu MATSUI , Yasushi ISHII , Digh HISAMOTO , Kan YASUI
IPC: H01L27/1157 , H01L29/423 , H01L21/28 , H01L29/792 , H01L29/66 , H01L27/02 , H01L29/51 , H01L29/06
CPC classification number: H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
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公开(公告)号：US20160336074A1
公开(公告)日：2016-11-17
申请号：US15224669
申请日：2016-08-01
Applicant: Renesas Electronics Corporation
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26 , H01L27/115 , H01L21/28 , G11C16/04 , G11C16/24
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
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公开(公告)号：US20140198577A1
公开(公告)日：2014-07-17
申请号：US14214969
申请日：2014-03-16
Inventor： Toshihiro TANAKA , Yukiko UMEMOTO , Mitsuru HIRAKI , Yutaka SHINAGAWA , Masamichi FUJITO , Kazufumi SUZUKAWA , Hiroyuki TANIKAWA , Takashi YAMAKI , Yoshiaki KAMIGAKI , Shinichi MINAMI , Kozo KATAYAMA , Nozomu MATSUZAKI
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc
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公开(公告)号：US20130277635A1
公开(公告)日：2013-10-24
申请号：US13927073
申请日：2013-06-25
Applicant: Renesas Electronics Corporation
Inventor： Satoru HANZAWA , Fumihiko NITTA , Nozomu MATSUZAKI , Toshihiro TANAKA
IPC: H01L45/00
CPC classification number: G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
Abstract: In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
Abstract translation: 在包括由可变电阻器使用存储元件的存储器单元和选择晶体管形成的存储单元阵列的半导体器件中，缓冲单元布置在读出放大器和存储单元阵列之间以及字驱动器和存储单元阵列之间 。 存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。 同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。 通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。
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