公开(公告)号：US20200343268A1

公开(公告)日：2020-10-29

申请号：US16928542

申请日：2020-07-14

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20170047403A1

公开(公告)日：2017-02-16

申请号：US15176146

申请日：2016-06-07

Applicant: Renesas Electronics Corporation

Inventor： Hidekazu ODA

IPC: H01L29/08 ,  H01L29/45 ,  H01L29/04 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02636 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78654

Abstract: An element isolation portion includes a projection portion that projects from an SOI substrate and comes into contact with a piled-up layer. The height of the upper surface of the projection portion is configured to be lower than or equal to the height of the upper surface of the piled-up layer and higher than or equal to a half of the height of the upper surface of the piled-up layer with reference to a surface of a silicon layer of the SOI substrate.

Abstract translation: 元件隔离部分包括从SOI衬底突出并与堆叠层接触的突出部分。 突起部的上表面的高度被构造成低于或等于堆积层的上表面的高度，并且高于或等于堆叠层的上表面的高度的一半， 参考SOI衬底的硅层的表面。

公开(公告)号：US20160005765A1

公开(公告)日：2016-01-07

申请号：US14855150

申请日：2015-09-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi SHINOHARA ,  Hidekazu ODA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

公开(公告)号：US20150194428A1

公开(公告)日：2015-07-09

申请号：US14662276

申请日：2015-03-19

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu OTA ,  Hirokazu SAYAMA ,  Hidekazu ODA

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20210313467A1

公开(公告)日：2021-10-07

申请号：US17353079

申请日：2021-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20200066757A1

公开(公告)日：2020-02-27

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180019260A1

公开(公告)日：2018-01-18

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20160087069A1

公开(公告)日：2016-03-24

申请号：US14864781

申请日：2015-09-24

Applicant: Renesas Electronics Corporation

Inventor： Hidekazu ODA

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L29/167 ,  H01L29/78 ,  H01L29/36 ,  H01L21/324

CPC classification number: H01L29/66068 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78687

Abstract: A semiconductor device includes an SOI substrate and a MISFET formed on the SOI substrate. The SOI substrate has a base substrate, a ground plane region formed on the base substrate, a BOX layer formed on the ground plane region and an SOI layer formed on the BOX layer. The base substrate is made of silicon and the ground plane region includes a semiconductor region made of silicon carbide.

Abstract translation: 半导体器件包括在SOI衬底上形成的SOI衬底和MISFET。 SOI衬底具有基底基板，形成在基底基板上的接地平面区域，形成在接地平面区域上的BOX层和形成在BOX层上的SOI层。 基底由硅制成，接地平面区域包括由碳化硅制成的半导体区域。

公开(公告)号：US20150364490A1

公开(公告)日：2015-12-17

申请号：US14739065

申请日：2015-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidekazu ODA

IPC: H01L27/12 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L29/6656 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.

Abstract translation: 为了提高具有完全耗尽的SOI晶体管的半导体器件的可靠性和性能，而形成在栅电极的侧壁上的偏移间隔物的宽度被配置为大于或等于半导体层的厚度并且更小 除了半导体层的厚度和绝缘膜的厚度的总和的厚度以外，杂质被离子注入到未被栅电极和偏移间隔物覆盖的半导体层中。 因此，通过离子注入杂质形成的延伸层不会从低于栅电极的端部的位置进入沟道。