公开(公告)号：US20210296165A1

公开(公告)日：2021-09-23

申请号：US17343448

申请日：2021-06-09

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/525 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20170358489A1

公开(公告)日：2017-12-14

申请号：US15670867

申请日：2017-08-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi MAESHIMA ,  Kotaro HORIKOSHI ,  Katsuhiko HOTTA ,  Toshiyuki TAKAHASHI ,  Hironori OCHI ,  Kenichi SHOJI

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/321 ,  H01L23/532 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/0209 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L29/66477 ,  H01L29/6659

Abstract: It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 μg/m3 and less.

公开(公告)号：US20150228579A1

公开(公告)日：2015-08-13

申请号：US14696365

申请日：2015-04-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract translation: 为了简化多层Cu互连的双镶嵌形成步骤，省略了在光致抗蚀剂膜下方的抗反射膜的形成步骤。 具体地说，用形成在其上的光致抗蚀剂膜作为掩模，干蚀刻层间绝缘膜，并且通过在形成在层间绝缘膜中的阻挡膜的表面处终止蚀刻来形成互连沟槽。 阻挡膜由具有低光反射率的SiCN膜制成，从而当曝光光致抗蚀剂膜时，其用作防反射膜。

公开(公告)号：US20140199831A1

公开(公告)日：2014-07-17

申请号：US14214975

申请日：2014-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20140038409A1

公开(公告)日：2014-02-06

申请号：US14042938

申请日：2013-10-01

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract translation: 为了简化多层Cu互连的双镶嵌形成步骤，省略了在光致抗蚀剂膜下方的抗反射膜的形成步骤。 具体地说，用形成在其上的光致抗蚀剂膜作为掩模，干蚀刻层间绝缘膜，并且通过在形成在层间绝缘膜中的阻挡膜的表面处终止蚀刻来形成互连沟槽。 阻挡膜由具有低光反射率的SiCN膜制成，从而当曝光光致抗蚀剂膜时，其用作防反射膜。