公开(公告)号：US20160365278A1

公开(公告)日：2016-12-15

申请号：US15147591

申请日：2016-05-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi MAESHIMA ,  Kotaro HORIKOSHI ,  Katsuhiko HOTTA ,  Toshiyuki TAKAHASHI ,  Hironori OCHI ,  Kenichi SHOJI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L21/311 ,  H01L21/3205

CPC classification number: H01L21/76879 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/0209 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76808 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L29/66477 ,  H01L29/6659

Abstract: It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 μg/m3 and less.

Abstract translation: 提供一种半导体器件的制造方法，包括以下步骤：在后表面上制备具有氮化硅膜的半导体衬底; 在所述半导体衬底的主表面上形成具有通孔的层间绝缘膜; 以及在所述通孔内选择性地形成通孔填充物。 该方法还包括以下步骤：执行晶片后表面清洁以暴露形成在半导体衬底的后表面上的氮化硅膜的表面; 然后在半导体衬底的主表面上的层间绝缘膜和通孔填充物上形成由化学放大型抗蚀剂制成的光致抗蚀剂膜，其中半导体衬底在铵离子浓度为1000μg的气氛中储存 / m3以下。

公开(公告)号：US20150200158A1

公开(公告)日：2015-07-16

申请号：US14592730

申请日：2015-01-08

Applicant: Renesas Electronics Corporation

Inventor： Ayaka OKUMURA ,  Katsuhiko HOTTA ,  Yoshinori KONDO ,  Hiroaki OSAKA

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/02 ,  H01L23/00 ,  H01L27/088 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L24/85 ,  H01L27/088 ,  H01L27/092 ,  H01L2224/02166 ,  H01L2224/05624 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/43 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/85375 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014

Abstract: Characteristics of a semiconductor device are improved. An opening that exposes a pad region of a top-layer wiring containing aluminum is formed in a protection film over the wiring, and aluminum nitride is formed on a surface of the exposed wiring. Additionally, a silicon nitride film is formed on a back surface of a semiconductor substrate having the wiring. As described above, foreign substances generated over the pad region due to the silicon nitride film on the back surface of the semiconductor substrate can be prevented by providing an aluminum nitride film over the pad region. Particularly, even in a case of requiring time before an inspection step and a bonding step, after a formation step of the pad region, formation reaction of the foreign substances can be prevented in the pad region, and the characteristics of the semiconductor device can be improved.

Abstract translation: 提高了半导体器件的特性。 在布线的保护膜上形成露出包含铝的顶层布线的焊盘区域的开口，并且在暴露的布线的表面上形成氮化铝。 此外，在具有布线的半导体衬底的背面上形成氮化硅膜。 如上所述，通过在焊盘区域上设置氮化铝膜，可以防止由于半导体衬底的背面上的氮化硅膜而在衬垫区域上产生的异物。 特别地，即使在检查步骤和接合步骤之前需要时间的情况下，在焊盘区域的形成步骤之后，可以在焊盘区域中防止异物的形成反应，并且半导体器件的特性可以 改进。

公开(公告)号：US20200211897A1

公开(公告)日：2020-07-02

申请号：US16817544

申请日：2020-03-12

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/525 ,  H01L21/8238

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20170271259A1

公开(公告)日：2017-09-21

申请号：US15616899

申请日：2017-06-07

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20160358853A1

公开(公告)日：2016-12-08

申请号：US15238471

申请日：2016-08-16

Applicant: Renesas Electronics Corporation

Inventor： Ayaka OKUMURA ,  Katsuhiko HOTTA ,  Yoshinori KONDO ,  Hiroaki OSAKA

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L23/528 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L24/85 ,  H01L27/088 ,  H01L27/092 ,  H01L2224/02166 ,  H01L2224/05624 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/43 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/85045 ,  H01L2224/85375 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014

Abstract: A semiconductor device includes a silicon nitride film formed above a front surface side of a semiconductor substrate, a first wiring formed above the silicon nitride film, a second wiring containing aluminum formed over the first wiring via a first insulating film, a second insulating film having an opening over the second wiring, and aluminum nitride formed over the second wiring at a bottom surface of the opening.

Abstract translation: 半导体器件包括在半导体衬底的正面侧形成的氮化硅膜，在氮化硅膜上方形成的第一布线，经由第一绝缘膜形成在第一布线上的含有铝的第二布线，具有 在第二布线上的开口，以及形成在开口的底表面上的第二布线上的氮化铝。

公开(公告)号：US20230187275A1

公开(公告)日：2023-06-15

申请号：US18164153

申请日：2023-02-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/525 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L21/76832 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5258 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20190088537A1

公开(公告)日：2019-03-21

申请号：US16169796

申请日：2018-10-24

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20160293542A1

公开(公告)日：2016-10-06

申请号：US15181995

申请日：2016-06-14

Applicant: Renesas Electronics Corporation

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76808 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

公开(公告)号：US20150194381A1

公开(公告)日：2015-07-09

申请号：US14666602

申请日：2015-03-24

Applicant: Renesas Electronics Corporation

Inventor： Takuro HOMMA ,  Katsuhiko HOTTA ,  Takashi MORIYAMA

IPC: H01L23/50 ,  H01L23/482

CPC classification number: H01L23/50 ,  H01L22/32 ,  H01L23/3192 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48624 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

Abstract translation: 在制造LSI或半导体集成电路器件时，组装器件（如树脂密封步骤）的步骤通常在高温（例如85〜130℃）的环境中进行电压施加试验， 高湿度（例如约80％RH）。 已经发现，在测试中施加正电压的铝基焊盘的上表面边缘部分处，从上膜分离氮化钛抗反射膜和在氮化钛膜中产生裂纹 通过由于通过密封树脂等的水分引起的电化学反应，以产生氮化钛膜的氧化和膨胀。 这些问题通过在铝基焊盘的周边区域以环或狭缝形状移除焊盘上的氮化钛膜来解决。

公开(公告)号：US20250046653A1

公开(公告)日：2025-02-06

申请号：US18922646

申请日：2024-10-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko HOTTA ,  Kyoko SASAHARA

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/525 ,  H01L23/528 ,  H01L23/532

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.