公开(公告)号：US09070564B2

公开(公告)日：2015-06-30

申请号：US14446878

申请日：2014-07-30

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L27/06 ,  H01L27/07 ,  H01L49/02

CPC classification number: H01L21/28008 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/24

Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.

Abstract translation: 金属栅电极和多晶硅电阻元件混合安装在同一半导体衬底中。 金属栅电极形成在第一栅极绝缘膜上，并且包括第一栅极金属膜和第一栅极硅膜。 多晶硅电阻元件包括形成在层叠图案上的硅膜图案，其包括第一层压绝缘膜，第一层压金属膜和第二层压绝缘膜。 第一层压绝缘膜和第一栅极绝缘膜由公共绝缘膜形成; 第一层压金属膜和第一栅极金属膜由共同的金属膜形成，并且硅固体图案和第一栅极硅膜由普通的硅膜形成。 在平面图中，硅膜图案的覆盖区包括在第二层压绝缘膜内。

公开(公告)号：US20140342539A1

公开(公告)日：2014-11-20

申请号：US14446878

申请日：2014-07-30

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/24

Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.

Abstract translation: 金属栅电极和多晶硅电阻元件混合安装在同一半导体衬底中。 金属栅电极形成在第一栅极绝缘膜上，并且包括第一栅极金属膜和第一栅极硅膜。 多晶硅电阻元件包括形成在层叠图案上的硅膜图案，其包括第一层压绝缘膜，第一层压金属膜和第二层压绝缘膜。 第一层压绝缘膜和第一栅极绝缘膜由公共绝缘膜形成; 第一层压金属膜和第一栅极金属膜由共同的金属膜形成，并且硅固体图案和第一栅极硅膜由普通的硅膜形成。 在平面图中，硅膜图案的覆盖区包括在第二层压绝缘膜内。

公开(公告)号：US12080716B2

公开(公告)日：2024-09-03

申请号：US18317500

申请日：2023-05-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L27/1207 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US11217682B2

公开(公告)日：2022-01-04

申请号：US16707985

申请日：2019-12-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaaki Shinohara

IPC: H01L29/66 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308

Abstract: Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.

公开(公告)号：US10756115B2

公开(公告)日：2020-08-25

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L21/8234 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US10510775B2

公开(公告)日：2019-12-17

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/8238

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US09666584B2

公开(公告)日：2017-05-30

申请号：US15216856

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

公开(公告)号：US10483114B2

公开(公告)日：2019-11-19

申请号：US15592279

申请日：2017-05-11

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/28 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/1157 ,  H01L21/321 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

Abstract: Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a MISFET is formed. At this time, over the semiconductor substrate located in the memory cell region, a control gate electrode and a memory gate electrode each for the memory cell are formed first. Then, an insulating film is formed so as to cover the control gate electrode and the memory gate electrode. Subsequently, the upper surface of the insulating film is polished to be planarized. Thereafter, a conductive film for the gate electrode of the MISFET is formed and then patterned to form a gate electrode or a dummy gate electrode for the MISFET in the peripheral circuit region.

公开(公告)号：US10074556B2

公开(公告)日：2018-09-11

申请号：US15180484

申请日：2016-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Shigeo Tokumitsu

IPC: H01L21/764 ,  H01L21/762 ,  H01L27/11526 ,  H01L21/311 ,  H01L21/308 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11546 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L21/764 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

公开(公告)号：US10032667B2

公开(公告)日：2018-07-24

申请号：US15424798

申请日：2017-02-04

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66

Abstract: When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished.