公开(公告)号：US20160035672A1

公开(公告)日：2016-02-04

申请号：US14777454

申请日：2013-03-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuo FUNAYA ,  Takayuki IGARASHI

IPC: H01L23/522 ,  H01L27/06 ,  H01L21/3205 ,  H01L49/02

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.

Abstract translation: 线圈CL1经由第一绝缘膜形成在半导体衬底SB上，形成第二绝缘膜以覆盖第一绝缘膜和线圈CL1，并且在第二绝缘膜上形成焊盘PD1。 在第二绝缘膜上形成有具有PD1部分露出的开口OP1的层叠膜LF，并且在层压绝缘膜上形成线圈CL2。 线圈CL2设置在线圈CL1上方，线圈CL2和线圈CL1彼此磁耦合。 层叠膜LF由氧化硅膜LF1，氮化硅膜LF2和树脂膜LF3构成。

公开(公告)号：US20240312969A1

公开(公告)日：2024-09-19

申请号：US18588091

申请日：2024-02-27

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Tatsuo KASAOKA ,  Yasutaka NAKASHIBA

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L24/48 ,  H01L2224/48195 ,  H01L2924/1206

Abstract: A semiconductor chip includes a semiconductor substrate and a multilayer wiring layer formed on the semiconductor substrate, and at least one layer of the multilayer wiring layer is formed with a conductive pattern. The conductive pattern is formed so as to continuously surround a lower inductor and an upper inductor in plan view.

公开(公告)号：US20240162144A1

公开(公告)日：2024-05-16

申请号：US18510633

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA ,  Tatsuo KASAOKA

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48464 ,  H01L2924/30101

Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer formed on the semiconductor substrate, a first wiring formed on the multilayer wiring layer and configured to be applied with a first potential, an upper inductor formed on the multilayer wiring layer and configured to be applied with a second potential different from the first potential, an inorganic insulating film formed on the multilayer wiring layer, the first wiring, and the upper inductor, and an organic insulating film formed on the inorganic insulating film and disposed so as to cover the inorganic insulating film located between the first wiring and the upper inductor in plan view. Here, between the first wiring and the upper inductor, an opening portion exposing a part of the upper surface of the inorganic insulating film is formed in the organic insulating film.

公开(公告)号：US20240096788A1

公开(公告)日：2024-03-21

申请号：US18344431

申请日：2023-06-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Tatsuo KASAOKA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5227 ,  H01L23/5283 ,  H01L23/53257

Abstract: A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

公开(公告)号：US20160372419A1

公开(公告)日：2016-12-22

申请号：US15150597

申请日：2016-05-10

Applicant: Renesas Electronics Corporation

Inventor： Yoshikazu TSUNEMINE ,  Takayuki IGARASHI

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a manufacturing method thereof are provided. A discontinued part, in which the interface between an interlayer insulating film and a passivation film is discontinued, is formed between a first wiring layer and a second wiring layer that are adjacent to each other with a space therebetween. Both the interlayer insulating film and the passivation film face an air gap in the discontinued part.

Abstract translation: 可以抑制产品尺寸的增加并且能够提高布线层之间的耐电压的半导体装置及其制造方法。 在层间绝缘膜和钝化膜之间的界面中断的中止部分形成在第一布线层和第二布线层之间，其间具有空间。 层间绝缘膜和钝化膜均面向中断部分的气隙。

公开(公告)号：US20250022794A1

公开(公告)日：2025-01-16

申请号：US18768246

申请日：2024-07-10

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L27/02

Abstract: A semiconductor device includes a semiconductor substrate, a first coil, a second coil, a third coil, and a fourth coil, an insulating layer, and a first shield. The semiconductor substrate has a device region and a peripheral region. The peripheral region is present around the device region in a plan view. The first coil and the second coil are arranged on the device region and are arranged in a first direction in a plan view. The third coil and the fourth coil are respectively opposed to the first coil and the second coil via the insulating layer. The first shield is arranged between the semiconductor substrate and the first and second coils and overlaps with the first coil and the second coil in a plan view. A width of the first shield in a second direction orthogonal to the first direction is larger than a width of the first coil in the second direction and a width of the second coil in the second direction. The first shield is electrically connected to a reference potential.

公开(公告)号：US20240429159A1

公开(公告)日：2024-12-26

申请号：US18666149

申请日：2024-05-16

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Takayuki IGARASHI

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/01

Abstract: Providing a semiconductor device that can suppress the heat generation in a transformer. The semiconductor device comprises first, second, third and fourth coils, a lead wire, and an insulating layer. The lead wire is formed on the same layer as the first and second coils. The first and second coils are adjacent to each other through the lead wire in a plan view and are electrically connected in series through the lead wire. The insulating layer covers the first and second coils, and the lead wire. The third coil is formed on the first coil so as to face the first coil through the insulating layer. The fourth coil is formed on the second coil so as to face the second coil through the insulating layer. The third and fourth coils are adjacent to each other in a plan view and are electrically connected to each other.

公开(公告)号：US20170317024A1

公开(公告)日：2017-11-02

申请号：US15616151

申请日：2017-06-07

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Takuo FUNAYA

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.