公开(公告)号：US20180061662A1

公开(公告)日：2018-03-01

申请号：US15789740

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Takuo FUNAYA ,  Takayuki Igarashi

IPC: H01L21/3205 ,  H01L21/02 ,  H01L21/66 ,  H01L27/06 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01L23/528 ,  H01L23/495

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.

公开(公告)号：US20220260504A1

公开(公告)日：2022-08-18

申请号：US17587357

申请日：2022-01-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuo FUNAYA

IPC: G01N21/95 ,  H01L23/00 ,  G01N21/88

Abstract: A reliability prediction method includes: calculating a change of each of a plurality of alloy phases at a bonding portion between an electrode pad and a bonding wire; setting a generation of a metal oxide phase caused by a corrosion reaction, based on an initial crack structure of the bonding portion; calculating an elastic strain energy at each of specified portions of the bonding portion; setting a progress of a crack, based on the elastic strain energy at each of the specified portions; and predicting a lifetime of the semiconductor device, based on a length of the crack due to the progress of the crack.

公开(公告)号：US20170317024A1

公开(公告)日：2017-11-02

申请号：US15616151

申请日：2017-06-07

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Takuo FUNAYA

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L23/5227 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53223 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

公开(公告)号：US20170194164A1

公开(公告)日：2017-07-06

申请号：US15462583

申请日：2017-03-17

Applicant: Renesas Electronics Corporation

Inventor： Takuo FUNAYA ,  Takayuki IGARASHI

IPC: H01L21/3205 ,  H01L49/02 ,  H01L21/02 ,  H01L21/66 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

公开(公告)号：US20180337124A1

公开(公告)日：2018-11-22

申请号：US16048408

申请日：2018-07-30

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Takuo FUNAYA

IPC: H01L23/522 ,  H01L25/16 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L27/06 ,  H01L27/12

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

公开(公告)号：US20180294239A1

公开(公告)日：2018-10-11

申请号：US15888846

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Kenji SAKATA ,  Toshihiko AKIBA ,  Takuo FUNAYA ,  Hideaki TSUCHIYA ,  Yuichi YOSHIDA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: There is a need to improve reliability of the semiconductor device.A semiconductor device includes a printed circuit board and a semiconductor chip mounted over the printed circuit board. The semiconductor chip includes a pad, an insulation film including an opening to expose part of the pad, and a pillar electrode formed over the pad exposed from the opening. The printed circuit board includes a terminal and a resist layer including an opening to expose part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the printed circuit board are coupled via a solder layer. Thickness h1 of the pillar electrode is measured from the upper surface of the insulation film. Thickness h2 of the solder layer is measured from the upper surface of the resist layer. Thickness h1 is greater than or equal to a half of thickness h2 and is smaller than or equal to thickness h2.

公开(公告)号：US20160035672A1

公开(公告)日：2016-02-04

申请号：US14777454

申请日：2013-03-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuo FUNAYA ,  Takayuki IGARASHI

IPC: H01L23/522 ,  H01L27/06 ,  H01L21/3205 ,  H01L49/02

CPC classification number: H01L21/3205 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L22/14 ,  H01L22/32 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/0688 ,  H01L28/10 ,  H01L2223/6655 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.

Abstract translation: 线圈CL1经由第一绝缘膜形成在半导体衬底SB上，形成第二绝缘膜以覆盖第一绝缘膜和线圈CL1，并且在第二绝缘膜上形成焊盘PD1。 在第二绝缘膜上形成有具有PD1部分露出的开口OP1的层叠膜LF，并且在层压绝缘膜上形成线圈CL2。 线圈CL2设置在线圈CL1上方，线圈CL2和线圈CL1彼此磁耦合。 层叠膜LF由氧化硅膜LF1，氮化硅膜LF2和树脂膜LF3构成。

公开(公告)号：US20150318245A1

公开(公告)日：2015-11-05

申请号：US14651643

申请日：2012-12-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi UCHIDA ,  Hirokazu NAGASE ,  Takuo FUNAYA

IPC: H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L23/66 ,  H01L23/64

CPC classification number: H01L23/5227 ,  H01L23/49575 ,  H01L23/528 ,  H01L23/645 ,  H01L23/66 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L27/0688 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series between the pad PD5 and the pad PD6, and the pad PD7 is electrically connected between the coil CL5 and the coil CL6. The coil magnetically coupled to the coil CL5 is formed just below the coil CL5, the coil magnetically coupled to the coil CL6 is formed just below the coil CL6, and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL5 and CL6, directions of induction current flowing in the coils CL5 and CL6 are opposed to each other in the coils CL5 and CL6.

Abstract translation: 在半导体衬底上形成线圈CL5和CL6以及焊盘PD5，PD6和PD7。 线圈CL5和线圈CL6串联地电连接在焊盘PD5和焊盘PD6之间，焊盘PD7电连接在线圈CL5和线圈CL6之间。 磁耦合到线圈CL5的线圈形成在线圈CL5的正下方，与线圈CL6磁性耦合的线圈形成在线圈CL6的正下方，并且它们串联连接。 当线圈CL5和CL6正下方的串联连接的线圈中流过电流时，线圈CL5和CL6中流过的感应电流的方向在线圈CL5和CL6中彼此相对。