公开(公告)号：US20240203844A1

公开(公告)日：2024-06-20

申请号：US18482235

申请日：2023-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamichi HOSOKAWA ,  Tatsuaki TSUKUDA ,  Yoshihiro MASUMURA

IPC: H01L23/495 ,  H01F17/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01F17/0006 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/06177 ,  H01L2224/48245

Abstract: A semiconductor device includes: a first chip mounting portion and a second chip mounting portion adjacent to each other in a first direction; a first semiconductor chip and a third semiconductor chip adjacent to each other in a second direction and mounted on the first chip mounting portion; and a second semiconductor chip mounted on the second chip mounting portion. The third semiconductor has: one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip. In plan view, the first and second transformers are arranged along a side facing the second semiconductor chip, and the one of more first transformers are arranged closer to the first semiconductor chip than the one of more second transformers.

公开(公告)号：US20240186224A1

公开(公告)日：2024-06-06

申请号：US18060680

申请日：2022-12-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro NISHIYAMA ,  Toshiyuki HATA ,  Tatsuaki TSUKUDA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49811 ,  H01L23/4952 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/18 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/182

Abstract: Improving a performance of a semiconductor device. A method of manufacturing the semiconductor device, including steps of: forming a first convex portion on a front surface of a chip mounting portion; and mounting a semiconductor chip on the front surface of the chip mounting portion via a conductive adhesive material. Here, the semiconductor chip includes: a main transistor forming portion in which a main transistor is formed; and a sense transistor forming portion in which a sense transistor is formed. Also, in the step for mounting the semiconductor chip on the chip mounting portion, the semiconductor chip is mounted on the front surface of the chip mounting portion such that the sense transistor forming portion of the semiconductor chip overlaps the first convex portion formed on the front surface of the chip mounting portion in the step for forming the first convex portion.

公开(公告)号：US20240170375A1

公开(公告)日：2024-05-23

申请号：US17993390

申请日：2022-11-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuaki TSUKUDA ,  Tomohiro NISHIYAMA ,  Toshiyuki HATA ,  Koichi HASEGAWA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/37 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40175 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/73265

Abstract: The on-resistance of a semiconductor device is reduced. A package structure composing the semiconductor device includes a die pad, a plurality of leads, a first semiconductor chip having a power transistor and mounted on the die pad, and a second semiconductor chip including a control circuit for controlling the power transistor and mounted on the first semiconductor chip. Here, a source pad of the first semiconductor chip is electrically connected to a first lead and a seventh lead of the plurality of leads via a clip made of a material which is copper as a main component, and the width (and cross-sectional area) of the clip is larger than the width (and diameter) of a wire in plan view.

公开(公告)号：US20180263108A1

公开(公告)日：2018-09-13

申请号：US15870837

申请日：2018-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuaki TSUKUDA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H03H7/01

CPC classification number: H05K1/0216 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/023 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/181 ,  H05K2201/0723 ,  H05K2201/09218 ,  H05K2201/093 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10151 ,  H05K2201/10689

Abstract: A wiring board of an electronic device includes: a board terminal connected to a semiconductor device (semiconductor component); a wire formed in a first wiring layer and electrically connected to the board terminal; a conductor pattern formed in a second wiring layer and electrically connected to the wire via a via wire; and another conductor pattern formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern and the another conductor pattern face each other with an insulating layer interposed therebetween, and an area of a region where the conductor pattern and the another conductor pattern face each other is larger than an area of the wire.