公开(公告)号：US20200185394A1

公开(公告)日：2020-06-11

申请号：US16786176

申请日：2020-02-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shibun TSUDA ,  Tomohiro YAMASHITA

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11573 ,  H01L29/792 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/28

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

公开(公告)号：US20170186764A1

公开(公告)日：2017-06-29

申请号：US15457685

申请日：2017-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki YAMAMOTO ,  Tomohiro YAMASHITA

IPC: H01L27/11573 ,  H01L49/02 ,  H01L29/78 ,  H01L21/28 ,  H01L21/324 ,  H01L27/11575 ,  H01L21/265

CPC classification number: H01L27/11573 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11575 ,  H01L28/20 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/792

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

公开(公告)号：US20160079305A1

公开(公告)日：2016-03-17

申请号：US14850690

申请日：2015-09-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki YAMAMOTO ,  Tomohiro YAMASHITA

IPC: H01L27/146 ,  H01L21/265 ,  H01L29/10 ,  H01L21/266

CPC classification number: H01L27/14689 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1463 ,  H01L27/14641 ,  H01L27/14643 ,  H01L29/1033

Abstract: To provide a semiconductor device having improved performance and reduce a production cost.The semiconductor device has a plurality of photodiodes placed in array form on the main surface of a semiconductor substrate, a p+ type semiconductor region surrounding each photodiode in plan view, and a plurality of transistors placed between the direction-Y adjacent photodiodes. A method of manufacturing the semiconductor device includes forming the p+ type semiconductor region by implanting a p type impurity into the semiconductor substrate through a mask layer opened at a p+ type semiconductor region formation region and implanting an n type impurity into the semiconductor substrate through the mask layer. In the latter step, in the main surface of the semiconductor substrate, an impurity ion is implanted into a region between photodiode formation regions adjacent in the Y direction but not into a region between the photodiode formation regions adjacent in the X direction.

Abstract translation: 提供具有改进的性能并降低生产成本的半导体器件。 该半导体器件具有以半导体衬底的主表面上的阵列形式放置的多个光电二极管，平面图中围绕每个光电二极管的p +型半导体区域以及置于方向Y相邻的光电二极管之间的多个晶体管。 制造半导体器件的方法包括：通过在p +型半导体区域形成区域开口的掩模层将p型杂质注入到半导体衬底中，并通过掩模层将n型杂质注入到半导体衬底中来形成p +型半导体区域 。 在后一步骤中，在半导体衬底的主表面中，杂质离子注入到在Y方向相邻的光电二极管形成区域之间的区域中，但不注入到在X方向相邻的光电二极管形成区域之间的区域中。

公开(公告)号：US20190172837A1

公开(公告)日：2019-06-06

申请号：US16269797

申请日：2019-02-07

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA ,  Tamotsu OGATA ,  Masamichi FUJITO ,  Tomoya SAITO

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/8238 ,  H01L49/02 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157 ,  H01L29/94 ,  H01L29/792 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/11573 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/94

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

公开(公告)号：US20160099286A1

公开(公告)日：2016-04-07

申请号：US14970345

申请日：2015-12-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki YAMAMOTO ,  Yukio NISHIDA ,  Tomohiro YAMASHITA

IPC: H01L27/146

CPC classification number: H01L27/14689 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76897 ,  H01L27/10876 ,  H01L27/14609 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14887 ,  H01L29/1091 ,  H01L29/42396

Abstract: The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that has a gate length larger than that of the gate electrode part.

Abstract translation: 在包括在形成图像拾取装置的多个像素中的每一个中的光电二极管的占有面积为（...）的情况下，通过防止在外围晶体管中产生1 / f噪声来提高半导体器件的性能 扩大了 在半导体器件中，放大晶体管的栅电极由有源区上的栅电极部分和覆盖有源区和元件隔离区之间的边界的大宽度部分和边界附近的有源区两者形成， 其栅极长度大于栅电极部分的栅极长度。