公开(公告)号：US20180090626A1

公开(公告)日：2018-03-29

申请号：US15657136

申请日：2017-07-22

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA

IPC: H01L29/792 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/28

CPC classification number: H01L29/792 ,  H01L21/28518 ,  H01L27/11568 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7851

Abstract: Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.

公开(公告)号：US20170200726A1

公开(公告)日：2017-07-13

申请号：US15366047

申请日：2016-12-01

Applicant: Renesas Electronics Corporation

Inventor： Shibun TSUDA ,  Tomohiro YAMASHITA

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: When a memory cell is formed over a first fin and a low breakdown voltage transistor is formed over a second fin, the depth of a first trench for dividing the first fins in a memory cell region is made larger than that of a second trench for dividing the second fins in a logic region. Thereby, in the direction perpendicular to the upper surface of a semiconductor substrate, the distance between the upper surface of the first fin and the bottom surface of an element isolation region in the memory cell region becomes larger than that between the upper surface of the second fin and the bottom surface of the element isolation region in the logic region.

公开(公告)号：US20170053931A1

公开(公告)日：2017-02-23

申请号：US15239193

申请日：2016-08-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki YAMAMOTO ,  Tomohiro YAMASHITA

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/324 ,  H01L21/28 ,  H01L21/265 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11575 ,  H01L28/20 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/792

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

Abstract translation: 提高了半导体器件的性能。 由硅制成的膜形成在半导体衬底上的电阻元件形成区域中，并且作为选自包含第14族元素和第18族元素的元素中的至少一种元素的杂质为 离子注入到膜中，并且形成由其中离子注入杂质的部分的膜形成的膜部分。 接下来，在半导体衬底上的存储器形成区域中形成具有电荷存储部分的绝缘膜，并且在绝缘膜上形成导电膜。

公开(公告)号：US20180308855A1

公开(公告)日：2018-10-25

申请号：US16019862

申请日：2018-06-27

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA

IPC: H01L27/11521 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157 ,  H01L21/8234 ,  H01L27/11573 ,  H01L29/78

CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L21/823431 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7855 ,  H01L29/792

Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

公开(公告)号：US20170062445A1

公开(公告)日：2017-03-02

申请号：US15213369

申请日：2016-07-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L21/823431 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7855 ,  H01L29/792

Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

Abstract translation: 半导体器件包括：作为半导体衬底的从半导体衬底的主表面突出的部分的鳍具有沿第一方向的宽度，并沿第二方向延伸; 控制栅极电极，其经由第一栅极绝缘膜布置在所述鳍片上并沿所述第一方向延伸; 以及存储栅电极，其经由第二栅极绝缘膜设置在所述鳍片上并沿所述第一方向延伸。 此外，通过具有大于第一栅极绝缘膜的膜厚度的第二栅极绝缘膜布置存储栅电极的区域中的鳍的宽度小于鳍的宽度，其中控制 栅极通过第一栅极绝缘膜布置。

公开(公告)号：US20200295018A1

公开(公告)日：2020-09-17

申请号：US16887011

申请日：2020-05-29

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA

IPC: H01L27/11521 ,  H01L27/11568 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.

公开(公告)号：US20190081057A1

公开(公告)日：2019-03-14

申请号：US16036324

申请日：2018-07-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro YAMASHITA

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L29/51 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

Abstract: On the upper surface of a fin projecting from the upper surface of a semiconductor substrate, there are formed a control gate electrode through a gate insulating film and a memory gate electrode through a gate insulating film. A semiconductor region is formed in the fin beside the control gate electrode. On the semiconductor region, an insulating film, a first interlayer insulating film, and a second interlayer insulating film are formed. A plug reaching the semiconductor region is formed in the second interlayer insulating film, the first interlayer insulating film, and the insulating film. A cap film is formed between the control gate electrode and the interlayer insulating film, and the plug is positioned also right above the cap film.

公开(公告)号：US20180315768A1

公开(公告)日：2018-11-01

申请号：US15904349

申请日：2018-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA ,  Tamotsu OGATA ,  Masamichi FUJITO ,  Tomoya SAITO

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L49/02

CPC classification number: H01L27/11573 ,  H01L21/28273 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/94

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

公开(公告)号：US20160172509A1

公开(公告)日：2016-06-16

申请号：US15048791

申请日：2016-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yukio NISHIDA ,  Tomohiro YAMASHITA

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/792 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/42344 ,  H01L29/66833

Abstract: To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left. Next, a silicon film is formed over the semiconductor substrate, then the silicon film is patterned in the memory cell region, and, in the peripheral circuit region, the silicon film is left so that an outer peripheral portion of the remaining metal film is covered with the silicon film. Subsequently, in the peripheral circuit region, the silicon film, the metal film, and the insulating film are patterned for forming an insulating film portion formed of the insulating film, a metal film portion formed of the metal film, and a conductive film portion formed of the silicon film.

Abstract translation: 提高半导体器件的性能。 在制造半导体器件的方法中，在其表面上形成有绝缘膜的半导体衬底上形成金属膜，然后在存储单元区域中去除金属膜，而在外围电路的一部分中 区域，剩下金属膜。 接下来，在半导体衬底上形成硅膜，然后在存储单元区域中对硅膜进行构图，并且在外围电路区域中留下硅膜使剩余金属膜的外周部分被覆盖 与硅膜。 随后，在外围电路区域中，图案化硅膜，金属膜和绝缘膜，以形成由绝缘膜形成的绝缘膜部分，由金属膜形成的金属膜部分和形成的导电膜部分 的硅膜。

公开(公告)号：US20150206920A1

公开(公告)日：2015-07-23

申请号：US14537633

申请日：2014-11-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki YAMAMOTO ,  Yukio NISHIDA ,  Tomohiro YAMASHITA

IPC: H01L27/148

CPC classification number: H01L27/14689 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76897 ,  H01L27/10876 ,  H01L27/14609 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14641 ,  H01L27/14812 ,  H01L27/14831 ,  H01L27/14887 ,  H01L29/1091 ,  H01L29/42396

Abstract: The performance of a semiconductor device is improved by preventing 1/f noise from being generated in a peripheral transistor, in the case where the occupation area of photodiodes, which are included in each of a plurality of pixels that form an image pickup device, is expanded. In the semiconductor device, the gate electrode of an amplification transistor is formed by both a gate electrode part over an active region and a large width part that covers the boundary between the active region and an element isolation region and the active region near the boundary and that. has a gate length larger than that of the gate electrode part.

Abstract translation: 在包括在形成图像拾取装置的多个像素中的每一个中的光电二极管的占有面积为（...）的情况下，通过防止在外围晶体管中产生1 / f噪声来提高半导体器件的性能 扩大了 在半导体器件中，放大晶体管的栅电极由有源区上的栅电极部分和覆盖有源区和元件隔离区之间的边界的大宽度部分和边界附近的有源区两者形成， 那。 栅极长度大于栅电极部分的栅极长度。