公开(公告)号：US20240395823A1

公开(公告)日：2024-11-28

申请号：US18795310

申请日：2024-08-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20230253456A1

公开(公告)日：2023-08-10

申请号：US18135426

申请日：2023-04-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

CPC classification number: H01L29/1083 ,  H01L21/74 ,  H01L21/84 ,  H01L21/265 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20170294513A1

公开(公告)日：2017-10-12

申请号：US15628925

申请日：2017-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20150061006A1

公开(公告)日：2015-03-05

申请号：US14459999

申请日：2014-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi SHINOHARA ,  Hidekazu ODA ,  Toshiaki IWAMATSU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Abstract translation: 在具有通过绝缘层形成在半导体衬底上的半导体层的SOI衬底中，在nMIS形成区域和pMIS形成区域中的每个半导体层中形成MISFET。 在供电区域中，去除半导体层和绝缘层。 在半导体基板中，形成p型半导体区域，以便包括nMIS形成区域和一个供电区域，并且形成n型半导体区域以便包括pMIS形成区域，而另一个 的供电区域。 在半导体衬底中，形成具有比p型半导体区域低的杂质浓度的p型阱，以便容纳p型半导体区域，并且具有比n型半导体的杂质浓度低的n型阱 区域形成为包含n型半导体区域。

公开(公告)号：US20150008522A1

公开(公告)日：2015-01-08

申请号：US14495178

申请日：2014-09-24

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L27/11

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1207 ,  H01L29/78648

Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

Abstract translation: 在包括SRAM存储单元的半导体器件的特性中实现了改进。 在其中设置形成SRAM的存取晶体管的有源区域中，p型半导体区域经由绝缘层设置，使得其底部和侧部与n型半导体区域接触。 因此，p型半导体区域与n型半导体区域pn隔离，并且存取晶体管的栅电极耦合到p型半导体区域。 耦合是通过共享插头实现的，该共用插头是从存取晶体管的栅极电极延伸到p型半导体区域上的不连续的导电膜。 结果，当存取晶体管处于导通状态时，用作背栅的p型半导体区域中的电位同时增加，以允许晶体管的导通电流增加。

公开(公告)号：US20140203364A1

公开(公告)日：2014-07-24

申请号：US14155708

申请日：2014-01-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Toshiaki IWAMATSU

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/78603 ,  H01L29/78684

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract translation: 具有在包括支撑衬底的SOI衬底上形成的n沟道MISFET的半导体器件，形成在支撑衬底上的绝缘层和形成在绝缘层上的硅层具有以下结构。 在栅电极的支撑基板上设置用于阈值调整的杂质区域，使得硅层含有碳。 可以通过半导体区域以这种方式调整阈值进行阈值调整。 此外，通过设置含有碳的硅层，即使当用于阈值调节的半导体区域的杂质扩散到穿过绝缘层的硅层时，通过注入到硅层中的碳使杂质失活。 结果，可以降低晶体管特性的波动，例如MISFET的阈值电压的波动。

公开(公告)号：US20230282647A1

公开(公告)日：2023-09-07

申请号：US18317500

申请日：2023-05-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834 ,  H01L27/1207 ,  H01L21/823418

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20220077191A1

公开(公告)日：2022-03-10

申请号：US17528585

申请日：2021-11-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuta TSUCHIYA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H03K17/687 ,  H01L29/06

Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

公开(公告)号：US20190043949A1

公开(公告)日：2019-02-07

申请号：US16150323

申请日：2018-10-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180219067A1

公开(公告)日：2018-08-02

申请号：US15925850

申请日：2018-03-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/74 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.