Abstract:
A circuit that includes a Darlington transistor pair having an input transistor and an output transistor configured to generate an output signal at an output node in response to an input signal received through an input node is disclosed. The circuit has a feedback coupling network coupled between the output node and the input node for feeding back to the input node a portion of an amplified version of the input signal that passes through the input transistor. The circuit further includes a bias feedback network that includes a bias transistor and a resistive network that consists of only resistive elements such that no inductors and no capacitors are provided within the bias feedback network.
Abstract:
A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.
Abstract:
The present disclosure provides a power amplifier controller for starting up, operating, and shutting down a power amplifier. The power amplifier controller includes current sense amplifier circuitry adapted to monitor a main current of the power amplifier. A bias generator is also included and adapted to provide a predetermined standby bias voltage and an operational bias voltage based upon a main current level sensed by the current sense amplifier circuitry. The power amplifier controller further includes a sequencer adapted to control startup and shutdown sequences of the power amplifier. In at least one embodiment, the power amplifier is a gallium nitride (GaN) device, and the main current level sensed is a drain current of the GaN device. Moreover, the bias generator is a gate bias generator provided that the power amplifier is a field effect transistor (FET) device.
Abstract:
An unbalanced linear power amplifier (PA) is disclosed having a quadrature coupler with a 90° phase input port, a 0° phase input port, an output termination port, and a signal output port. Each of the 90° phase input port, the 0° phase input port, the output termination port, and the signal output port have a characteristic resistance (Ro). Also included is a first PA having an output coupled to a 90° phase input port of the quadrature coupler and a second PA having an output coupled to a 0° phase input port of the quadrature coupler. Biasing circuitry provides the first PA and the second PA with a similar gain. A tuning network is coupled between the output termination port and ground. The tuning network has an isolation resistance in series with an isolation inductance, wherein the isolation resistance is between about 0.02*Ro Ω and 0.8*Ro Ω.
Abstract:
Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.
Abstract:
A reconfigurable load modulation amplifier having a carrier amplifier and a peak amplifier that are coupled in parallel is disclosed. The peak amplifier provides additional power amplification when the carrier amplifier is driven into saturation. A quadrature coupler coupled between the carrier amplifier and the peak amplifier is configured to combine power from both the carrier amplifier and the peak amplifier for output through an output load terminal. The reconfigurable load modulation amplifier further includes control circuitry coupled to an isolation port of the quadrature coupler and configured to provide adjustable impedance at the isolation port of the quadrature coupler. As such, impedance at the isolation port of the quadrature coupler is tunable such that at least a carrier or peak amplifier is presented with a quadrature coupler load impedance that ranges from around about half an output load termination impedance to around about twice the output load termination impedance.
Abstract:
A reconfigurable load modulation amplifier having a carrier amplifier and a peak amplifier that are coupled in parallel is disclosed. The peak amplifier provides additional power amplification when the carrier amplifier is driven into saturation. A quadrature coupler coupled between the carrier amplifier and the peak amplifier is configured to combine power from both the carrier amplifier and the peak amplifier for output through an output load terminal. The reconfigurable load modulation amplifier further includes control circuitry coupled to an isolation port of the quadrature coupler and configured to provide adjustable impedance at the isolation port of the quadrature coupler. As such, impedance at the isolation port of the quadrature coupler is tunable such that at least a carrier or peak amplifier is presented with a quadrature coupler load impedance that ranges from around about half an output load termination impedance to around about twice the output load termination impedance.
Abstract:
Radio frequency (RF) amplification devices are disclosed that include Doherty amplification circuits and control circuits along with methods of operating the same. In one embodiment, the Doherty amplification circuit includes a quadrature coupler having an isolation port and a tunable impedance load coupled to the isolation port and configured to provide a tunable impedance. The control circuit is configured to tune the tunable impedance of the tunable impedance load at the isolation port dynamically as a function of the RF power of the Doherty amplification circuit. In this manner, the control circuit can provide dynamic load modulation, thereby increasing the power efficiency of the Doherty amplification circuit, particularly at backed-off power levels. The load modulation provided by the control circuit also allows the Doherty amplification circuit to provide broadband amplification in various RF communication bands.
Abstract:
Radio frequency (RF) amplification devices are disclosed that include Doherty amplification circuits and methods of operating the same. In one embodiment, a Doherty amplification circuit includes a main carrier RF amplifier, a peaking RF amplifier, and a periodic quadrature coupler. To provide Doherty amplification, the peaking RF amplifier is configured to be deactivated while an RF signal is below a threshold level and is configured to be activated while the RF signal is above the threshold level. The periodic quadrature coupler is configured to combine a first RF split signal from the main carrier RF amplifier and a second RF split signal from the peaking RF amplifier into the RF signal, such that the RF signal is output from an output port while the peaking RF amplifier is activated. The periodic quadrature coupler allows the Doherty amplification circuit to provide broadband amplification in various RF communication bands.
Abstract:
A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.