Abstract:
Methods and apparatus are presented for sampling low side inverter phase currents, in which current sampling is selectively delayed in a given PWM cycle by a non-zero sampling delay time value from a nominal sample time if the middle pulse width value is less than a non-zero first threshold to facilitate adequate signal settling for accurate current measurement, and if a middle total continuous on-time near the end of the given PWM cycle is less than a non-zero second threshold, the middle total continuous on-time is selectively extended by adding a non-zero adjustment offset time value to a middle pulse width value for a next PWM cycle.
Abstract:
For calculating load resistance, a pulse generation module drives a pulse width modulation (PWM) inverter in response to a control voltage. The PWM inverter includes a U phase pole, a V phase pole, and a W phase pole. Each U, V, and W phase pole includes an upper pole device and a lower pole device. The PWM inverter turns off the U phase pole, turns on the W upper pole device, turns off the W lower pole device, and applies the control voltage to the V upper pole device and the V lower pole device. A forward drop correction module corrects the control voltage based on a feedforward compensation voltage determined from a forward voltage drop. A load resistance module calculates a load resistance for a load based on an average control voltage, an average bus voltage, and an average load feedback current.
Abstract:
Power conversion systems, methods and control apparatus to operate a power converter, including a processor computes an angle of an AC output current signal, compute a first voltage error that represents an inverter switch dead time voltage error in a synchronous reference frame according to the angle, computes a compensated voltage command according to the first voltage error and according to a voltage control reference, and controls an inverter according to the compensated voltage command.
Abstract:
The present techniques include methods and systems for operating converter to maintain a lifespan of the converter. In some embodiments, the operating frequency of the converter may be increased such that stress may be reduced on the bond wires of the converter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the converter operating in a maximum power point tracking (MPPT) mode and determining whether the MPPT operation results in aging the converter to a point which reduces the converter lifespan below a desired lifespan. If the MPPT operation reduces the converter lifespan below the desired lifespan, the frequency of the converter may be increased such that the converter may be controlled to operate at a percentage of MPPT. Thus, in some embodiments, power output may be optimized with respect to maintaining a desired lifespan of the converter.
Abstract:
A double fed induction generator (DFIG) converter, methods and computer readable mediums are presented in which rotor side current spikes are attenuated by selectively activating at least one series damping circuit to conduct current through a series damping circuit resistance coupled in series between one or more DFIG rotor leads and a grid side converter in response to a grid fault occurrence or a grid fault clearance, and selectively bypassing the series damping circuit resistance after activating the series damping circuit.
Abstract:
Present embodiments relate to a method for synchronizing an electric grid. The method includes receiving a phase voltage of the electric grid. The method further includes determining one or more disturbance frequencies in the phase voltage via a plurality of sequential tracking filters, wherein each of the plurality of tracking filters corresponds to a harmonic of the received phase voltage. The method further includes removing the disturbance frequencies components sequentially to produce a minimally distorted frequency, and performing a PLL operation on the clean frequency to determine a phase angle of the frequency.
Abstract:
A phase angle detector with a PLL, a power converter, and a method for reducing offsets in an input signal, in which an adaptive offset processor selectively removes a DC offset component from the input signal to generate a modified signal including a fundamental frequency component and higher order harmonics of the input signal with the DC offset component removed, and the PLL provides a phase angle signal at least partially according to the modified signal.
Abstract:
A system and method for controlling an electrical device is provided. The method comprises receiving three phase power from a source, decomposing signals representative of power in each phase of the three phase power to provide a positive-sequence component of each phase and tracking the positive-sequence component of each phase via a phase locked loop and a tracking filter.
Abstract:
A system and method for controlling an electrical device is provided. The method comprises receiving three phase power from a source, decomposing signals representative of power in each phase of the three phase power to provide a positive-sequence component of each phase and tracking the positive-sequence component of each phase via a phase locked loop and a tracking filter.