公开(公告)号：US20060012394A1

公开(公告)日：2006-01-19

申请号：US11189209

申请日：2005-07-26

申请人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0094

摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

公开(公告)号：US06867616B1

公开(公告)日：2005-03-15

申请号：US10455773

申请日：2003-06-04

申请人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong H. Lee ,  Rakesh Patel

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03D3/24

CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： In a programmable logic device (“PLD”), a serial interface incorporating phase-locked loops (“PLLs”) is provided with connections that allow one or more of the PLLs to be used as general purpose PLLs in the PLD. The connections include conductors to allow reference clock signals from the PLD logic core, or from outside the PLL, to be used by the PLLS, as well as conductors that allow the PLD core to control the phases of the PLLs. For some of the PLLs, conductors to allow the PLL output clock to be used by the PLD are also provided, where such output conductors do not normally exist in such a serial interface.

摘要翻译： 在可编程逻辑器件（“PLD”）中，集成了锁相环（“PLL”）的串行接口具有允许一个或多个PLL用作PLD中的通用PLL的连接。 这些连接包括允许来自PLD逻辑核心或PLL外部的参考时钟信号由PLLS使用的导体以及允许PLD内核控制PLL相位的导体。 对于一些PLL，还提供允许PLD使用PLL输出时钟的导体，其中这种输出导体通常不存在于这种串行接口中。

公开(公告)号：US08994425B2

公开(公告)日：2015-03-31

申请号：US13566882

申请日：2012-08-03

申请人： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

发明人： Ramanand Venkata ,  Henry Lui ,  Arch Zaliznyak

IPC分类号： H03L7/00 ,  H03K5/1534

CPC分类号： H03K5/1534

摘要： A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

摘要翻译： 一个电路包括第一和第二对准器电路和一个去歪斜电路。 第一对准器电路可操作以将第一输入串行数据信号与控制信号对准以产生第一对准的串行数据信号。 第二对准器电路可操作以将第二输入串行数据信号与控制信号对准以产生第二对准的串行数据信号。 去偏置电路可操作以减少第一和第二对准的串行数据信号之间的偏差，以产生第一和第二输出串行数据信号。

公开(公告)号：US08570197B2

公开(公告)日：2013-10-29

申请号：US12953766

申请日：2010-11-24

申请人： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

发明人： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC分类号： H03M9/00

CPC分类号： H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

摘要翻译： 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US07656187B2

公开(公告)日：2010-02-02

申请号：US11288810

申请日：2005-11-28

申请人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

发明人： Thungoc Tran ,  Sergey Yuryevich Shumarayev ,  Tim Tri Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

摘要翻译： 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

公开(公告)号：US07646217B2

公开(公告)日：2010-01-12

申请号：US11539006

申请日：2006-10-05

申请人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

发明人： Ramanand Venkata ,  Rakesh H. Patel ,  Chong H. Lee

IPC分类号： H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17784

摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

摘要翻译： 在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。 设备上的部分或全部功能块被补充有串行接口。 尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。 这意味着设备功耗的显着降低。 串行接口可以与全局设备时钟（例如PLL）同步工作。 在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口 块将不得不更复杂，因为它们必须能够与外部设备异步操作。

公开(公告)号：US07436210B2

公开(公告)日：2008-10-14

申请号：US11655797

申请日：2007-01-18

申请人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

发明人： Ramanand Venkata ,  Rakesh H Patel ,  Chong H Lee

IPC分类号： H03K19/173

CPC分类号： G06F13/385

摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

摘要翻译： 在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

公开(公告)号：US20070188189A1

公开(公告)日：2007-08-16

申请号：US11539006

申请日：2006-10-05

申请人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

发明人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17784

摘要： In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.

摘要翻译： 在可编程逻辑器件中，部分或全部并行互连资源由器件内的串行互连资源代替。 设备上的部分或全部功能块被补充有串行接口。 尽管这使得功能块更加复杂，但它允许显着减少互连资源消耗的面积。 这意味着设备功耗的显着降低。 串行接口可以与全局设备时钟（例如PLL）同步工作。 在某些情况下，可以省略输入/输出块中提供的用于外部信号的串行接口，因为功能块中的串行接口也可以接管外部串行接口功能，尽管在这些情况下，功能中的串行接口 块将不得不更复杂，因为它们必须能够与外部设备异步操作。

公开(公告)号：US07151470B1

公开(公告)日：2006-12-19

申请号：US10969450

申请日：2004-10-20

申请人： Ning Xue ,  Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

发明人： Ning Xue ,  Ramanand Venkata ,  Chong H Lee ,  Rakesh Patel

IPC分类号： H03M7/00

CPC分类号： H03M7/04

摘要： A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

摘要翻译： 用于填充协议接口的数据转换器或“变速箱”可以执行多个不同的转换，例如在64位和66位之间，在24位和26位之间，或在48位和50位之间。 这是通过使用可允许用户选择时钟速度的可编程分频器从不同时钟速度对齿轮箱进行计时的，这些时钟速度全部来自相同的主时钟（可以从接收机实施例中的数据恢复）。 当转换不是设计齿轮箱的最大宽度的转换时，未使用的位将被忽略。 转换器还可以在不同宽度的数据中找到用于对齐目的的填充位，当数据不是设计转换器的最宽时，再次忽略未使用的位。

公开(公告)号：US20060233172A1

公开(公告)日：2006-10-19

申请号：US11177034

申请日：2005-07-08

申请人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

IPC分类号： H04L12/28

CPC分类号： H03K19/17744

摘要： A serial interface for a programmable logic device can be operated according to various communications protocols and includes both a receiver portion and a transmitter portion. The receiver portion includes at least a word or byte alignment stage, a de-skew stage, a rate compensation or matching stage, a padded protocol decoder stage (e.g., 8B/10B decoder circuitry or 64B/66B decoder circuitry), a byte deserializer stage, a byte reorder stage, and a phase compensation stage. The transmitter portion includes at least a phase compensation stage, a byte deserializer stage, and a padded protocol encoder stage (e.g., an 8B/10B encoder circuitry or 64B/66B encoder circuitry). Each stage may have multiple occurrences of relevant circuitry. Selection circuitry, such as multiplexers, selects the appropriate stages, and circuitry within each stage, for the protocol being used.