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    Synchronous wired-OR ACK status for memory with variable write latency
    13.
    发明授权
    Synchronous wired-OR ACK status for memory with variable write latency 有权

    公开(公告)号：US11101393B2

    公开(公告)日：2021-08-24

    申请号：US16673431

    申请日：2019-11-04

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

    IPC: H01L31/0236 ,  G06F3/06 ,  G06F13/372 ,  G06F13/16 ,  G06F12/02 ,  G06F12/00

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    Synchronous wired-OR ACK status for memory with variable write latency
    14.
    发明授权
    Synchronous wired-OR ACK status for memory with variable write latency 有权

    公开(公告)号：US10468544B2

    公开(公告)日：2019-11-05

    申请号：US15369244

    申请日：2016-12-05

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  Eric Linstadt ,  Jun Kim

    IPC: G06F12/02 ,  H01L31/0236 ,  G06F13/16 ,  G06F3/06 ,  G06F13/372 ,  G06F12/00

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    Phase Calibration of Clock Signals
    16.
    发明申请
    Phase Calibration of Clock Signals 有权
    时钟信号的相位校准

    公开(公告)号：US20170005785A1

    公开(公告)日：2017-01-05

    申请号：US15176864

    申请日：2016-06-08

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H04L7/00

    CPC classification number: H04L7/033 ,  H03L7/081 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/0337 ,  H04L25/03

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    Abstract translation: 具有时钟相位校准的接收器。 第一采样电路基于输入信号，由第一时钟信号控制的第一采样电路的采样相位产生第一数字数据。 第二采样电路基于输入信号产生第二数字数据，由第二时钟信号控制的第二采样电路的采样相位。 接收机内的电路校准不同阶段的时钟。 在第一校准阶段期间，在选择第一数字数据以产生输出数据的同时调整第二时钟信号的相位。 在第二校准阶段期间，在为输出数据路径选择第一数字数据的同时调整第一时钟信号的相位。

    Supporting Calibration For Sub-Rate Operation In Clocked Memory Systems
    18.
    发明申请
    Supporting Calibration For Sub-Rate Operation In Clocked Memory Systems 有权
    支持时钟存储系统中子速率操作的校准

    公开(公告)号：US20150310903A1

    公开(公告)日：2015-10-29

    申请号：US14687739

    申请日：2015-04-15

    Applicant: Rambus Inc.

    Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

    Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

    Phase calibration of clock signals
    20.
    发明授权
    Phase calibration of clock signals 有权

    公开(公告)号：US10367636B2

    公开(公告)日：2019-07-30

    申请号：US16156868

    申请日：2018-10-10

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H03L7/081 ,  H04L7/00 ,  H04L25/03 ,  H04L25/02

    Abstract: A receiver with clock phase calibration is disclosed. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

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