NOR and NAND Memory Arrangement of Resistive Memory Elements
    16.
    发明申请
    NOR and NAND Memory Arrangement of Resistive Memory Elements 有权
    NOR和NAND内存排列的电阻式存储元件

    公开(公告)号:US20070242496A1

    公开(公告)日:2007-10-18

    申请号:US11737236

    申请日:2007-04-19

    IPC分类号: G11C11/00

    摘要: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

    摘要翻译: 存储器装置包括:用于施加参考电压的第一线,用于施加工作电压的第二线和多个电阻性存储器元件,每个元件包括电阻存储器单元和MOS存储单元选择晶体管。 NOR存储器配置配置有每个存储器元件,其包括与连接到第一线路的晶体管串联连接的电阻存储器单元和选择晶体管,以及连接到第二线路的存储器单元。 NAND存储器配置配置有一系列形成链的电阻存储元件,每个存储元件包括并联连接的电阻存储单元和选择晶体管。 链条连接到布置在面向选择晶体管的存储单元的一侧上的第一行,而第二行设置在远离选择晶体管的存储单元的一侧。

    NOR and NAND memory arrangement of resistive memory elements
    17.
    发明授权
    NOR and NAND memory arrangement of resistive memory elements 有权
    NOR和NAND存储器布置的电阻存储器元件

    公开(公告)号:US07746683B2

    公开(公告)日:2010-06-29

    申请号:US11737236

    申请日:2007-04-19

    IPC分类号: G11C11/00

    摘要: A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

    摘要翻译: 存储器装置包括:用于施加参考电压的第一线,用于施加工作电压的第二线和多个电阻性存储器元件,每个元件包括电阻存储器单元和MOS存储单元选择晶体管。 NOR存储器配置配置有每个存储器元件,其包括与连接到第一线路的晶体管串联连接的电阻存储器单元和选择晶体管,以及连接到第二线路的存储器单元。 NAND存储器配置配置有一系列形成链的电阻存储元件,每个存储元件包括并联连接的电阻存储单元和选择晶体管。 链条连接到布置在面向选择晶体管的存储单元的一侧上的第一行,而第二行设置在远离选择晶体管的存储单元的一侧。

    Use of polybenzoxazoles (PBOS) for adhesion

    公开(公告)号:US07052936B2

    公开(公告)日:2006-05-30

    申请号:US10208397

    申请日:2002-07-30

    IPC分类号: H01L21/44 H01L21/48 H01L21/50

    CPC分类号: C09J179/06

    摘要: The present invention describes the use of polybenzoxazoles (PBOs) for adhesively bonding articles or materials, especially components used in the semiconductor industry, such as chips and wafers, a process for adhesively bonding materials, especially chips and wafers, chip and/or wafer stacks produced by the process, and adhesive compositions which comprise the polybenzoxazoles of the formula (I).