公开(公告)号：US5943571A

公开(公告)日：1999-08-24

申请号：US883571

申请日：1997-06-26

Applicant: Herbert Schaefer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

Inventor： Herbert Schaefer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

IPC: C23C16/04 ,  H01L21/033 ,  H01L21/20 ,  H01L21/205 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  C23C16/04 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0334 ,  H01L27/11517 ,  H01L29/66825

Abstract: For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.

Abstract translation: 为了制造精细结构，使用在载气中使用含有SiH 4和GeH 4的第一工艺气体时，在CVD工艺的基板的表面上形成限定精细结构的尺寸的核。 核可以同时用作掩模，例如蚀刻或注入时，以及保留在结构中的有源或无源部件，例如作为电荷存储在EEPROM的电介质中。

公开(公告)号：US5817553A

公开(公告)日：1998-10-06

申请号：US766977

申请日：1996-12-16

Applicant: Reinhard Stengl ,  Martin Franosch ,  Hermann Wendt

Inventor： Reinhard Stengl ,  Martin Franosch ,  Hermann Wendt

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively etched with respect to the first material. Layered structures are formed from the sequence of layers, with the flanks of the layered structures each having a conductive support structure. The layered structures are formed with openings, such as gaps, in which the surface of the layers is exposed. The layers made of the second material are selectively removed with respect to the layers made of the first material. The exposed surface of the layers made of the first material and of the support structure are provided with a capacitor dielectric, onto which a counter-electrode is placed. The capacitor is made by etching p.sup.- -doped polysilicon that is selective to p.sup.+ -doped polysilicon.

Abstract translation: 制造用于动态存储单元配置的电容器，特别是用于动态存储单元配置的层叠电容器，是通过首先形成一层层而制成的，该层包括由与第二材料制成的层交替的第一导电材料制成的层。 可以相对于第一材料选择性地蚀刻第二材料。 层状结构由层序列形成，层状结构的侧面各自具有导电支撑结构。 层状结构形成有诸如间隙的开口，其中层的表面暴露在其中。 由第二材料制成的层相对于由第一材料制成的层选择性地去除。 由第一材料和支撑结构制成的层的暴露表面设置有电容器电介质，其上放置有相对电极。 电容器是通过蚀刻对p +掺杂多晶硅有选择性的p掺杂多晶硅制成的。

公开(公告)号：US20050006723A1

公开(公告)日：2005-01-13

申请号：US10912344

申请日：2004-08-04

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schafer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schafer ,  Martin Franosch

IPC: H01L21/331 ,  H01L29/732 ,  H01L31/0328

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US06867105B2

公开(公告)日：2005-03-15

申请号：US10215152

申请日：2002-08-08

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US07612430B2

公开(公告)日：2009-11-03

申请号：US10297421

申请日：2001-06-15

Applicant: Martin Franosch ,  Thomas Meister ,  Herbert Schäfer ,  Reinhard Stengl ,  Konrad Wolf

Inventor： Martin Franosch ,  Thomas Meister ,  Herbert Schäfer ,  Reinhard Stengl ,  Konrad Wolf

IPC: H01L29/732

CPC classification number: H01L29/1004

Abstract: The silicon bipolar transistor (100) comprises a base, with a first highly-doped base layer (105) and a second poorly-doped base layer (106) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer (106).

Abstract translation: 硅双极晶体管（100）包括具有一起形成基极的第一高掺杂基极层（105）和第二较差掺杂的基极层（106）的基极。 发射极是完全高度掺杂的，直接安装在第二基极层（106）上。

公开(公告)号：US06197666B1

公开(公告)日：2001-03-06

申请号：US09390496

申请日：1999-09-03

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Hans Reisinger ,  Matthias Ilg

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Hans Reisinger ,  Matthias Ilg

IPC: H01L2120

CPC classification number: H01L27/10873 ,  C23C16/24 ,  C23C16/56 ,  H01L21/28035 ,  H01L21/32055 ,  H01L21/76877

Abstract: A method for the fabrication of a doped silicon layer, includes carrying out deposition by using a process gas containing SiH4, Si2H6 and a doping gas. The doped silicon layer which is thus produced can be used both as a gate electrode of an MOS transistor and as a conductive connection. At a thickness between 50 and 200 nm it has a resistivity less than or equal to 0.5 m&OHgr;cm.

Abstract translation: 一种用于制造掺杂硅层的方法，包括通过使用含有SiH 4，Si 2 H 6和掺杂气体的工艺气体进行沉积。 由此制造的掺杂硅层既可以用作MOS晶体管的栅电极，也可以用作导电连接。 在50至200nm的厚度之间，其电阻率小于或等于0.5mOMEGAcm。

公开(公告)号：US20090011556A9

公开(公告)日：2009-01-08

申请号：US09948010

申请日：2001-09-05

Applicant: Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

Inventor： Gerhard Beitel ,  Wolfgang Hoenlein ,  Reinhard Stengl ,  Elke Fritsch ,  Siegfried Schwarzl ,  Hermann Wendt

IPC: H01L21/00 ,  H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/02071 ,  H01L21/32136 ,  H01L28/55

Abstract: A method for producing a microelectronic structure is suggested in which a layer structure (30) which partially covers a substrate (5) and which comprises at least one first conductive layer (15,20) which reaches to a side wall (35) of the layer structure (30), is covered with a second conductive layer (45). The second conductive layer (45) is then subsequently back-etched to as great an extent as possible with an etching process with physical delamination, wherein delaminated material deposits on the side wall (35) of the layer structure (30). On the side wall (35) the delaminated material forms a protection layer (60) by means of which the first conductive layer (15,20) is to be protected from attack by oxygen to the furthest extent possible.

公开(公告)号：US6165835A

公开(公告)日：2000-12-26

申请号：US341937

申请日：1999-07-20

Applicant: Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

Inventor： Hermann Wendt ,  Hans Reisinger ,  Andreas Spitzer ,  Reinhard Stengl ,  Ulrike Gruning ,  Josef Willer ,  Wolfgang Honlein ,  Volker Lehmann

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10861 ,  H01L29/66181 ,  Y10S438/96

Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

Abstract translation: PCT No.PCT / DE98 / 00089 Sec。 371日期1999年7月20日 102（e）1999年7月20日PCT 1998年1月12日PCT PCT。 出版物WO98 / 32166 日期1998年7月23日在制造硅电容器中，在硅衬底（1）中形成孔结构（2），其表面通过掺杂形成导电区（3），并且其表面设置有电介质 层（4）和导电层（5），而不填充孔结构（2）。 为了补偿通过掺杂导电区（3）实现的硅衬底（1）上的机械应变，在导电层（5）的表面上形成共形辅助层（6），该辅助层在下面 压缩机械应力。

公开(公告)号：US06887437B1

公开(公告)日：2005-05-03

申请号：US09718902

申请日：2000-11-22

Applicant: Volker Lehmann ,  Stefan Ottow ,  Reinhard Stengl ,  Hans Reisinger ,  Hermann Wendt

Inventor： Volker Lehmann ,  Stefan Ottow ,  Reinhard Stengl ,  Hans Reisinger ,  Hermann Wendt

IPC: B01D50/00 ,  B01D53/34 ,  B01J19/00 ,  C23C16/02 ,  C23C16/26

CPC classification number: C23C16/26 ,  B01J19/0093 ,  B01J2219/00788 ,  B01J2219/00822 ,  B01J2219/00824 ,  B01J2219/00828 ,  B01J2219/00835 ,  B01J2219/00844 ,  B01J2219/00862 ,  C23C16/0245

Abstract: A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into an interior of the silicon wafer, preferably as far as a second main area of the silicon wafer. A catalyst layer at least partly covers the surface of the pores.

Abstract translation: 反应器构造包含连接到硅晶片的壳体。 硅晶片具有从硅晶片的第一主区域延伸到硅晶片的内部的孔，优选地直到硅晶片的第二主区域。 催化剂层至少部分地覆盖孔的表面。

公开(公告)号：US06614575B1

公开(公告)日：2003-09-02

申请号：US09636521

申请日：2000-08-10

Applicant: Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

Inventor： Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

IPC: G02F103

CPC classification number: B82Y20/00 ,  G02B6/1225

Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

Abstract translation: 光学结构包括具有半导体材料和光栅结构的衬底。 光栅结构具有发射至少一个频带的特性，使得具有来自该频带的频率的光不能在光栅结构中传播。 光栅结构具有孔和缺陷区的构造。 孔以周期性阵列设置在缺陷区域的外侧，并且周期性阵列在缺陷区域中受到干扰。 光栅结构的表面至少在缺陷区域附近设置有导电层。 还提供了一种用于制造光学结构的方法。