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    Method of operating a storage cell arrangement
    2.
    发明授权
    Method of operating a storage cell arrangement 失效
    操作存储单元布置的方法

    公开(公告)号：US6040995A

    公开(公告)日：2000-03-21

    申请号：US230614

    申请日：1999-01-28

    申请人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    发明人： Hans Reisinger ,  Ulrike Gruning ,  Hermann Wendt ,  Reinhard Stengl ,  Volker Lehmann ,  Josef Willer ,  Martin Franosch ,  Herbert Schafer ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Thomas Bohm

    IPC分类号： H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02

    CPC分类号： H01L29/513 ,  H01L29/518 ,  H01L29/792

    摘要： For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

    摘要翻译： PCT No.PCT / DE97 / 01601 Sec。 371日期1999年1月28日 102（e）1999年1月28日PCT PCT 1997年7月29日PCT公布。 出版物WO98 / 06140 日期1998年2月12日对于具有MOS晶体管的存储单元布置的操作，作为包含具有第一氧化硅层（51）的介电三层（5）的存储单元，具有氮化硅层（52）和第二氧化硅 层（53）作为栅极电介质，由此氧化硅层​​分别为至少3nm厚，将第一截止电压值分配给第一逻辑值，并将MOS晶体管的第二截止电压值分配给第二逻辑值 用于存储数字数据。 存储在存储单元中的信息可以通过施加相应的电压电平来修改，尽管由于氧化硅层的厚度，不可能完全去除存储在氮化硅层中的电荷。 当修改截止电压时，利用的是电介质三层中的电场由存储在氮化硅层中的电荷而失真。

    Method for fabricating a capacitor for a semiconductor memory configuration
    3.
    发明授权
    Method for fabricating a capacitor for a semiconductor memory configuration 有权
    制造半导体存储器配置的电容器的方法

    公开(公告)号：US6117790A

    公开(公告)日：2000-09-12

    申请号：US302655

    申请日：1999-04-30

    申请人： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

    发明人： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

    摘要： A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

    摘要翻译： 一种制造用于半导体存储器配置的电容器的方法。 在这种情况下，将可选择的可蚀刻材料施加到导电支撑件，该导电支撑件通过绝缘体层中的接触孔连接到半导体本体并且被图案化。 在其上施加第一导电层并图案化。 在第一导电层中引入一个孔，通过该孔蚀刻可选择性蚀刻的材料。 在该过程中在第一导电层下方产生空腔。 空腔的内表面和第一导电层的外表面设置有电介质层，第二导电层被施加并图案化。

    Method for fabricating a dopant region
    4.
    发明授权
    Method for fabricating a dopant region 有权
    掺杂剂区域的制造方法

    公开(公告)号：US6133126A

    公开(公告)日：2000-10-17

    申请号：US398688

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

    CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

    摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

    摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

    Manufacturing method for a capacitor in an integrated storage circuit
    6.
    发明授权
    Manufacturing method for a capacitor in an integrated storage circuit 有权
    集成存储电路中电容器的制造方法

    公开(公告)号：US6127220A

    公开(公告)日：2000-10-03

    申请号：US312571

    申请日：1999-05-14

    申请人： Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

    发明人： Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

    摘要翻译： 在载体上施加层序列，其包含由第一导电材料和第二材料制成的交替层，其中两种材料都不同于载体材料。 在层序列中形成开口，其中填充有导电材料，从而产生中心支撑结构。 然后根据电容器的尺寸构造层序列，并且选择性地去除由第二材料制成的层，从而形成第一电容器电极。 层序列可以具有特别的p + - / p-硅层或硅/锗层。 也可以将蚀刻停止层作为最低层或第二层加入。

    Electrically programmable non-volatile memory cell configuration
    9.
    发明授权
    Electrically programmable non-volatile memory cell configuration 有权
    电可编程非易失性存储单元配置

    公开(公告)号：US06215140B1

    公开(公告)日：2001-04-10

    申请号：US09398691

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L2972

    CPC分类号： H01L21/8229 ,  H01L27/1021

    摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

    摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

    Bipolar transistor
    10.
    发明申请
    Bipolar transistor 有权
    双极晶体管

    公开(公告)号：US20050006723A1

    公开(公告)日：2005-01-13

    申请号：US10912344

    申请日：2004-08-04

    申请人： Reinhard Stengl ,  Thomas Meister ,  Herbert Schafer ,  Martin Franosch

    发明人： Reinhard Stengl ,  Thomas Meister ,  Herbert Schafer ,  Martin Franosch

    IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L31/0328

    CPC分类号： H01L29/66287 ,  H01L29/7322

    摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

    摘要翻译： 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。