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68 条记录 (耗时 0.03 秒)

    Method for manufacturing a solar cell from a substrate wafer
    3.
    发明授权
    Method for manufacturing a solar cell from a substrate wafer 失效
    从基板晶片制造太阳能电池的方法

    公开(公告)号：US5306647A

    公开(公告)日：1994-04-26

    申请号：US998611

    申请日：1992-12-30

    申请人： Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Wolfgang Hoenlein ,  Josef Willer

    发明人： Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Wolfgang Hoenlein ,  Josef Willer

    IPC分类号： C25F3/12 ,  H01L21/3063 ,  H01L31/0352 ,  H01L31/047 ,  H01L31/18

    CPC分类号： H01L31/1804 ,  H01L21/3063 ,  H01L31/03529 ,  H01L31/047 ,  Y02E10/547 ,  Y02P70/521

    摘要： A self-supporting layer of n-doped monocrystalline silicon is stripped from a substrate wafer of n-doped, monocrystalline silicon by electrochemical etching for manufacturing a solar cell. Holes are formed in the substrate wafer by electrochemical etching, particularly in a fluoride-containing, acidic electrolyte wherein the substrate wafer is connected as an anode. When a depth of the holes that essentially corresponds to the thickness of the self-supporting layer is reached, the process parameters of the etching are modified such that the self-supporting layer is stripped as a consequence of the holes growing together. The solar cell is manufactured from the self-supporting layer, and the method can be applied repeatedly on the same substrate wafer for stripping a plurality of self-supporting layers.

    摘要翻译： 通过用于制造太阳能电池的电化学蚀刻，从n掺杂的单晶硅的衬底晶片剥离n掺杂单晶硅的自支撑层。 通过电化学蚀刻，特别是在其中衬底晶片作为阳极连接的含氟化物的酸性电解质中，在衬底晶片中形成孔。 当达到基本上对应于自支撑层的厚度的孔的深度时，蚀刻的工艺参数被修改，使得自支撑层由于孔一起生长而被剥离。 该太阳能电池由自支撑层制造，并且可以在相同的基板晶片上重复地施加该方法以剥离多个自支撑层。

    Method for manufacturing rod-shaped silicon structures
    6.
    发明授权
    Method for manufacturing rod-shaped silicon structures 失效
    棒状硅结构的制造方法

    公开(公告)号：US5449310A

    公开(公告)日：1995-09-12

    申请号：US222597

    申请日：1994-04-04

    申请人： Reinhard Stengl ,  Wolfgang Hoenlein

    发明人： Reinhard Stengl ,  Wolfgang Hoenlein

    IPC分类号： H01J1/304 ,  H01J9/02 ,  H01J21/10 ,  H01J1/30

    CPC分类号： H01J1/3042 ,  H01J21/105 ,  H01J9/025 ,  H01J2201/30403 ,  H01J2201/30407

    摘要： Rod-shaped or cylindrical structures in the nm range on a substrate of silicon are manufactured. A first cylinder of silicon is selectively epitaxially deposited in the hole of a mask layer of oxide, and the mask layer is removed. The silicon is then oxidized to form an oxide layer having such a thickness that a thinner, second cylinder of silicon having practically the same height as the first cylinder remains. In a last step, this oxide layer is removed, so that the second cylinder forms a freestanding silicon rod on the surface of the substrate.

    摘要翻译： 制造在硅衬底上的nm范围内的棒状或圆柱形结构。 硅的第一圆柱体被选择性地外延沉积在氧化物的掩模层的孔中，并且去除掩模层。 然后将硅氧化以形成具有这样厚度的氧化物层，使得具有与第一气缸几乎具有相同高度的较薄的第二硅柱体保持不变。 在最后一步中，去除该氧化物层，使得第二圆柱体在基底表面上形成独立的硅棒。

    Electrically programmable non-volatile memory cell configuration
    7.
    发明授权
    Electrically programmable non-volatile memory cell configuration 有权
    电可编程非易失性存储单元配置

    公开(公告)号：US06215140B1

    公开(公告)日：2001-04-10

    申请号：US09398691

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L2972

    CPC分类号： H01L21/8229 ,  H01L27/1021

    摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

    摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

    Method for fabricating a dopant region
    8.
    发明授权
    Method for fabricating a dopant region 有权
    掺杂剂区域的制造方法

    公开(公告)号：US6133126A

    公开(公告)日：2000-10-17

    申请号：US398688

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

    CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

    摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

    摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。