公开(公告)号：US20190096902A1

公开(公告)日：2019-03-28

申请号：US16188499

申请日：2018-11-13

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L29/423 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11568 ,  H01L23/535 ,  H01L27/11573 ,  H01L29/42344

Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1

公开(公告)号：US20190088670A1

公开(公告)日：2019-03-21

申请号：US16032388

申请日：2018-07-11

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L29/423

CPC classification number: H01L27/11573 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/823481 ,  H01L23/5329 ,  H01L27/11526 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L2027/11831

Abstract: In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.

公开(公告)号：US20170271162A1

公开(公告)日：2017-09-21

申请号：US15404463

申请日：2017-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA ,  Tatsuyoshi MIHARA

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/311 ,  H01L29/792 ,  H01L21/3105 ,  H01L27/1157 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L21/31051 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792

Abstract: Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage portion. A dummy control gate electrode is formed so as to be adjacent to the memory gate electrode via a second insulating film. The memory and the dummy control gate electrodes are made of different materials. A third insulating film is formed so as to cover the memory and the dummy control gate electrodes and then polished to expose the memory and the dummy control gate electrodes. Then, etching is performed under a condition in which the memory gate electrode is less likely to be etched than the dummy control gate electrode to remove the dummy control gate electrode. Then, in a trench as a region from which the dummy control gate electrode is removed, a control gate electrode for the memory cell is formed.

公开(公告)号：US20160293620A1

公开(公告)日：2016-10-06

申请号：US15043576

申请日：2016-02-14

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode. Between the memory gate electrode and the semiconductor substrate, in a region where the second insulating film is not formed, another silicon dioxide film is embedded.

Abstract translation: 在具有非易失性存储器的半导体器件的性能方面获得了改进。 非易失性存储器的存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极和经由第二绝缘膜形成在半导体衬底上的存储栅电极，该第二绝缘膜经由第二绝缘膜与控制栅电极相邻 。 第二绝缘膜包括由二氧化硅膜制成的第三绝缘膜，在第三绝缘膜上形成由氮化硅膜制成的第四绝缘膜，以及在第四绝缘膜上的第五绝缘膜。 第五绝缘膜包括氮氧化硅膜。 在存储栅电极和半导体衬底之间，第四绝缘膜和第五绝缘膜的相应端部比存储栅电极的下表面的端部更靠近存储栅电极的侧表面。 在存储栅电极和半导体衬底之间，在没有形成第二绝缘膜的区域中嵌入另一个二氧化硅膜。

公开(公告)号：US20200212057A1

公开(公告)日：2020-07-02

申请号：US16813699

申请日：2020-03-09

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L27/11568 ,  H01L29/51 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

公开(公告)号：US20180315768A1

公开(公告)日：2018-11-01

申请号：US15904349

申请日：2018-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA ,  Tamotsu OGATA ,  Masamichi FUJITO ,  Tomoya SAITO

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L49/02

CPC classification number: H01L27/11573 ,  H01L21/28273 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/94

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

公开(公告)号：US20180061964A1

公开(公告)日：2018-03-01

申请号：US15792423

申请日：2017-10-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi TOKITA ,  Tamotsu OGATA

IPC: H01L29/66 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode.

公开(公告)号：US20180053778A1

公开(公告)日：2018-02-22

申请号：US15786944

申请日：2017-10-18

Applicant: Renesas Electronics Corporation

Inventor： Tamotsu OGATA

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/792

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

公开(公告)号：US20160218108A1

公开(公告)日：2016-07-28

申请号：US14973471

申请日：2015-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi TOKITA ,  Tamotsu OGATA

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode.

Abstract translation: 提高了具有非易失性存储器的半导体器件的可靠性。 非易失性存储器的存储单元是分离栅型，并且在半导体衬底中具有第一和第二n型半导体区域，经由第一绝缘膜形成在半导体区域之间的衬底上的控制电极和存储栅电极 通过具有电荷累积部分的第二绝缘膜在半导体区域之间的衬底上形成。 SSI方法用于写入存储单元。 在存储单元的读取操作期间，第一和第二半导体区域分别用作源区和漏区。 与存储栅电极的侧表面相邻形成的第一侧壁间隔物的第一宽度大于与控制栅电极的侧表面相邻形成的第二侧壁间隔件的第二宽度。