公开(公告)号：US20070038919A1

公开(公告)日：2007-02-15

申请号：US11495550

申请日：2006-07-31

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C29/00

CPC分类号： G06F11/1044 ,  G11C2029/0409

摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

摘要翻译： 提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。 将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。 除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。 通过这种方式，可以更换制造过程中发生的错误。 此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。

公开(公告)号：US07603592B2

公开(公告)日：2009-10-13

申请号：US11495550

申请日：2006-07-31

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C29/00

CPC分类号： G06F11/1044 ,  G11C2029/0409

摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

摘要翻译： 提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。 将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。 除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。 通过这种方式，可以更换制造过程中发生的错误。 此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。

公开(公告)号：US20080094922A1

公开(公告)日：2008-04-24

申请号：US11924353

申请日：2007-10-25

申请人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C7/1027 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/028 ,  G11C2207/002

摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

摘要翻译： 提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。 在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。 在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。 电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时， 随后的突发读取周期。 因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

公开(公告)号：US07619911B2

公开(公告)日：2009-11-17

申请号：US10579911

申请日：2003-11-21

申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

公开(公告)号：US20060193160A1

公开(公告)日：2006-08-31

申请号：US11354131

申请日：2006-02-15

申请人： Satoru Hanzawa ,  Riichiro Takemura ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Riichiro Takemura ,  Kazuhiko Kajigaya

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.

摘要翻译： 将不同相位的控制时钟分配到划分为多个存储体的存储器阵列，并且在不同阶段执行条目和搜索关键字的处理（读取和写入操作和搜索操作）。 划分为存储体的存储器阵列进一步分成较小的阵列，即子阵列，并且读写搜索电路块中的读出放大器由两个子阵列共享。 在这种情况下，采用所谓的开放位线结构，其中每个位线都从两个子阵列连接到读出放大器。 相同的查找表被注册到多个存储体，连续输入的搜索键被顺序地输入到多个存储体，并且与不同相位的控制时钟同步地执行搜索操作。

公开(公告)号：US20050056876A1

公开(公告)日：2005-03-17

申请号：US10975494

申请日：2004-10-29

申请人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

发明人： Shinichi Miyatake ,  Kazuhiko Kajigaya ,  Kazuyuki Miyazawa ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/119

CPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10897 ,  Y10S257/905 ,  Y10S257/906

摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.

摘要翻译： 提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低， 高速读出时间，确保自刷新时间长的刷新周期。 采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域 形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。

公开(公告)号：US06538912B2

公开(公告)日：2003-03-25

申请号：US10139330

申请日：2002-05-07

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

IPC分类号： G11C1100

CPC分类号： H01L27/10894 ,  G11C11/4097 ,  H01L27/10897

摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

公开(公告)号：US06400596B2

公开(公告)日：2002-06-04

申请号：US09725107

申请日：2000-11-29

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Katsutaka Kimura ,  Kazuhiko Kajigaya ,  Tsugio Takahashi

IPC分类号： G11C1100

CPC分类号： H01L27/10894 ,  G11C11/4097 ,  H01L27/10897

摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

摘要翻译： 当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线 内存阵列 因此，提供了根据本发明的半导体器件。 在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统 放置 即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。 由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

公开(公告)号：US07388768B2

公开(公告)日：2008-06-17

申请号：US11354131

申请日：2006-02-15

申请人： Satoru Hanzawa ,  Riichiro Takemura ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Riichiro Takemura ,  Kazuhiko Kajigaya

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is further divided into smaller arrays, that is, sub-arrays, and a sense amplifier in a read-write-search circuit block is shared by the two sub-arrays. In this case, a so-called open bit line structure in which each one bit line is connected from both sub-arrays to a sense amplifier is adopted. The same look-up table is registered to multiple banks, successively inputted search keys are sequentially inputted to the multiple banks, and the search operation is carried out in synchronization with the control clocks of different phases.

摘要翻译： 将不同相位的控制时钟分配到划分为多个存储体的存储器阵列，并且在不同阶段执行条目和搜索关键字的处理（读取和写入操作和搜索操作）。 划分为存储体的存储器阵列进一步分成较小的阵列，即子阵列，并且读写搜索电路块中的读出放大器由两个子阵列共享。 在这种情况下，采用所谓的开放位线结构，其中每个位线都从两个子阵列连接到读出放大器。 相同的查找表被注册到多个存储体，连续输入的搜索键被顺序地输入到多个存储体，并且与不同相位的控制时钟同步地执行搜索操作。

公开(公告)号：US20070274144A1

公开(公告)日：2007-11-29

申请号：US10579911

申请日：2003-11-21

申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

IPC分类号： G11C7/00

CPC分类号： G11C15/04 ,  G11C15/043

摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。