公开(公告)号：US08000103B2

公开(公告)日：2011-08-16

申请号：US12339583

申请日：2008-12-19

申请人： Robert J. Lipp ,  Phillip P. Hughes

发明人： Robert J. Lipp ,  Phillip P. Hughes

IPC分类号： H05K7/20 ,  G06F1/20

CPC分类号： F28D15/0266 ,  F28D1/05316 ,  F28D15/00 ,  F28D2021/0031 ,  F28F9/002 ,  F28F2255/02 ,  F28F2275/08 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K7/20818 ,  H01L2924/00

摘要： Various embodiments disclose a system and method to provide cooling to electronic components, such as electronic modules or the like. The system includes one or more cold plates that are configured to be thermally coupled to one or more of the electronic components. Internally, each of the cold plates has a cooling fluid flowing inside of at least one passageway. The cooling fluid thus removes heat from the electronic components primarily by conductive heat transfer. An input and an output header are attached to opposite ends of the passageway to allow entry and exit of the cooling fluid. The input and output headers are attached to an external system to circulate the cooling fluid.

摘要翻译： 各种实施例公开了向电子部件（例如电子模块等）提供冷却的系统和方法。 该系统包括被配置为热耦合到一个或多个电子部件的一个或多个冷板。 在内部，每个冷板具有在至少一个通道内流动的冷却流体。 因此，冷却流体主要通过导电热传递从电子部件移除热量。 输入和输出头部附接到通道的相对端，以允许冷却流体的进入和离开。 输入和输出接头连接到外部系统以使冷却液循环。

公开(公告)号：US5371457A

公开(公告)日：1994-12-06

申请号：US679457

申请日：1991-04-02

申请人： Robert J. Lipp

发明人： Robert J. Lipp

IPC分类号： G01R31/30 ,  G01R27/02

CPC分类号： G01R31/3008 ,  G01R31/3004

摘要： Various methods and apparatus perform IDDQ testing using the input and output circuits typically associated with input and output pads of an integrated circuit. Under these methods, the number of tester channels and external circuit elements required for IDDQ measurements is minimized. In one embodiment, the IDDQ current is measured by sensing the voltage at either an input pad or an output pad. In another embodiment, an internal pull-up transistor of known resistance is used for current sensing. In another embodiment, a method and apparatus for performing IDDQ testing quickly are provided by disconnecting the primary power or ground bus line connections from the tester and using alternate connections to provide power to the circuit under test over the duration of the IDDQ testing.

摘要翻译： 各种方法和装置使用通常与集成电路的输入和输出焊盘相关联的输入和输出电路进行IDDQ测试。 在这些方法下，IDDQ测量所需的测试仪通道和外部电路元件的数量被最小化。 在一个实施例中，通过感测输入焊盘或输出焊盘处的电压来测量IDDQ电流。 在另一个实施例中，已知电阻的内部上拉晶体管用于电流检测。 在另一个实施例中，用于通过断开主电源或接地总线线路连接与测试器的连接来提供用于快速执行IDDQ测试的方法和装置，并且在IDDQ测试的持续时间内使用备用连接来向待测电路提供电力。

公开(公告)号：US5347177A

公开(公告)日：1994-09-13

申请号：US4364

申请日：1993-01-14

申请人： Robert J. Lipp

发明人： Robert J. Lipp

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H04L25/02 ,  H03K17/16 ,  H03K19/0175

CPC分类号： H04L25/0292 ,  H03K19/0005 ,  H03K19/00361 ,  H03K19/01728 ,  H03K19/01855 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0298

摘要： This invention provides a means to interconnect high performance CMOS VLSI circuits. LTL (a coined descriptor for describing a novel CMOS interface standard) offers improved performance by providing active threshold control of an input buffer to speed signal capture, and by controlling performance limiting characteristics of signal reflection, ground bounce, receiver overdriving and ringing. These performance limiting characteristics are controlled by providing: level-sensitive impedance control of an output driver, distributed active line termination using impedances of input buffers on a transmission line, and balanced loading using closed-loop transmission lines.

摘要翻译： 本发明提供了一种互连高性能CMOS VLSI电路的手段。 LTL（用于描述新型CMOS接口标准的创建描述符）通过提供输入缓冲器的主动阈值控制来加速信号捕获，并通过控制信号反射，接地反弹，接收器过驱动和振铃的性能限制特性来提供改进的性能。 这些性能限制特性通过提供：输出驱动器的电平敏感阻抗控制，使用传输线上的输入缓冲器的阻抗的分布式有源线终端以及使用闭环传输线的平衡负载来控制。

公开(公告)号：US4937826A

公开(公告)日：1990-06-26

申请号：US242848

申请日：1988-09-09

申请人： Tushar R. Gheewala ,  Robert J. Lipp

发明人： Tushar R. Gheewala ,  Robert J. Lipp

IPC分类号： G01R31/26 ,  G01R31/30 ,  G01R31/316 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  H01L21/66

CPC分类号： G01R31/316 ,  G01R31/30 ,  G01R31/318516

摘要： An apparatus for testing for faults in an integrated circuit is attached to sense lines which are coupled to output nodes of logic gates of a test structure within an integrated circuit, such as a "Cross-Check" test structure built into an integrate circuit apparatus. A related method provide precharging of the sense lines to a known signal level prior to using the sense lines to sense the signal level at a test point. The apparatus combined with sense amplifiers or comparators attached to the sense lines may adjust detection levels of the comparators synchronously to test for either an output "one" minimum level (VOH) or output "zero" maximum level (VOL) to test for other classes of faults. The apparatus attached to the sense lines may inject charge into an output node of a logic gate at preselected times in a test sequence to modify the signal level at that output node to test for faults. A method according to the invention includes path sensitization whereby test patterns can be reduced to Boolean expressions.

摘要翻译： 用于测试集成电路中的故障的装置附接到感测线，感测线耦合到集成电路内的测试结构的逻辑门的输出节点，例如内置于集成电路装置中的“交叉检验”测试结构。 相关方法在使用感测线在感测测试点处的信号电平之前，将感测线预充电到已知的信号电平。 与传感线连接的读出放大器或比较器的设备可以同步调整比较器的检测电平，以测试输出“一”最小电平（VOH）或输出“零”最大电平（VOL），以测试其他类 的故障。 附接到感测线的装置可以在测试序列中的预选时间将电荷注入逻辑门的输出节点，以修改该输出节点处的信号电平以测试故障。 根据本发明的方法包括路径敏化，其中测试图案可以减少到布尔表达式。

公开(公告)号：US20190254199A1

公开(公告)日：2019-08-15

申请号：US15894657

申请日：2018-02-12

申请人： Robert J. Lipp ,  Phillip N. Hughes

发明人： Robert J. Lipp ,  Phillip N. Hughes

IPC分类号： H05K7/20 ,  H05K7/14

摘要： A system and an method to provide cooling of electronic components mounted in a tray by means of a cold plate, is disclosed. The system comprises a cold plate that is mounted in a rack with removable trays mounted on rails affixed to the underside of the cold plate. In one embodiment, compatibility with Open Rack specifications developed by the Open Compute Project is disclosed.

公开(公告)号：US20120037339A1

公开(公告)日：2012-02-16

申请号：US13210309

申请日：2011-08-15

申请人： Robert J. Lipp ,  Phillip P. Hughes

发明人： Robert J. Lipp ,  Phillip P. Hughes

IPC分类号： F28F13/00

CPC分类号： F28D15/0266 ,  F28D1/05316 ,  F28D15/00 ,  F28D2021/0031 ,  F28F9/002 ,  F28F2255/02 ,  F28F2275/08 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K7/20818 ,  H01L2924/00

摘要： Various embodiments disclose a system and method to provide cooling to electronic components, such as electronic modules or the like. The system includes one or more cold plates that are configured to be thermally coupled to one or more of the electronic components. Internally, each of the cold plates has a cooling fluid flowing inside of at least one passageway. The cooling fluid thus removes heat from the electronic components primarily by conductive heat transfer. An input and an output header are attached to opposite ends of the passageway to allow entry and exit of the cooling fluid. The input and output headers are attached to an external system to circulate the cooling fluid.

摘要翻译： 各种实施例公开了向电子部件（例如电子模块等）提供冷却的系统和方法。 该系统包括被配置为热耦合到一个或多个电子部件的一个或多个冷板。 在内部，每个冷板具有在至少一个通道内流动的冷却流体。 因此，冷却流体主要通过导电热传递从电子部件移除热量。 输入和输出头部附接到通道的相对端，以允许冷却流体的进入和离开。 输入和输出接头连接到外部系统以循环冷却液。

公开(公告)号：US20090159241A1

公开(公告)日：2009-06-25

申请号：US12339583

申请日：2008-12-19

申请人： Robert J. Lipp ,  Phillip P. Hughes

发明人： Robert J. Lipp ,  Phillip P. Hughes

IPC分类号： F28F7/00 ,  F28F3/12

CPC分类号： F28D15/0266 ,  F28D1/05316 ,  F28D15/00 ,  F28D2021/0031 ,  F28F9/002 ,  F28F2255/02 ,  F28F2275/08 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K7/20818 ,  H01L2924/00

摘要： Various embodiments disclose a system and method to provide cooling to electronic components, such as electronic modules or the like. The system includes one or more cold plates that are configured to be thermally coupled to one or more of the electronic components. Internally, each of the cold plates has a cooling fluid flowing inside of at least one passageway. The cooling fluid thus removes heat from the electronic components primarily by conductive heat transfer. An input and an output header are attached to opposite ends of the passageway to allow entry and exit of the cooling fluid. The input and output headers are attached to an external system to circulate the cooling fluid.

摘要翻译： 各种实施例公开了向电子部件（例如电子模块等）提供冷却的系统和方法。 该系统包括被配置为热耦合到一个或多个电子部件的一个或多个冷板。 在内部，每个冷板具有在至少一个通道内流动的冷却流体。 因此，冷却流体主要通过导电热传递从电子部件移除热量。 输入和输出头部附接到通道的相对端，以允许冷却流体的进入和离开。 输入和输出接头连接到外部系统以循环冷却液。

公开(公告)号：US06751238B1

公开(公告)日：2004-06-15

申请号：US09553501

申请日：2000-04-20

申请人： Robert J. Lipp ,  Phillip P. Hughes

发明人： Robert J. Lipp ,  Phillip P. Hughes

IPC分类号： H04J1408

CPC分类号： H04J3/062 ,  H04J3/0691 ,  H04J2203/0005

摘要： A large network switch has switch elements distributed across several chassis separated by perhaps several hundred meters. A generated sync pulse arrives at different switch elements at different times, creating skew. The latency of data through the network switch is set to match the frame period of SONET frames. SONET frames are adjusted at the ingress ports to align the data pointer to the beginning of the frame. The frame is divided along row boundaries into separate cell-packets that are routed across the switch fabric to the egress port. The packets are held in a buffer at the egress port until the next frame begins with the next sync pulse. Upon receiving the next sync pulse, the frame is transmitted. No pointer adjustment is needed by the egress port. A row number is used as a sequence number for the cell-packet to allow the egress port to re-order the cell-packets when transmitting the frame. Since no pointer manipulation is needed at the egress port, pointer management is simplified.

摘要翻译： 一个大型网络交换机的交换机元件分布在几个机架上，分隔几百米。 产生的同步脉冲在不同时间到达不同的开关元件，产生偏斜。 通过网络交换机的数据延迟设置为与SONET帧的帧周期相匹配。 SONET帧在入口端口进行调整，以将数据指针与帧的开头对齐。 该帧沿着行边界划分成分离的单元包，该数据包通过交换结构路由到出口端口。 分组被保存在出口端口的缓冲器中，直到下一帧以下一个同步脉冲开始。 一旦接收到下一个同步脉冲，则发送该帧。 出口端口不需要调整指针。 使用行号作为信元分组的序列号，以允许出口端口在发送帧时重新排序信元分组。 由于在出口端口不需要指针操作，简化了指针管理。

公开(公告)号：US06594261B1

公开(公告)日：2003-07-15

申请号：US09470144

申请日：1999-12-22

申请人： Younes Boura ,  Robert J. Lipp ,  Rene L. Cruz

发明人： Younes Boura ,  Robert J. Lipp ,  Rene L. Cruz

IPC分类号： H04L1228

CPC分类号： H04L45/00 ,  H04L41/0654 ,  H04L43/0811 ,  H04L45/28 ,  H04L49/25 ,  H04L49/254 ,  H04L49/557

摘要： An interconnection network routes packets among switches connected in a multi-dimensional network of links. Each packet contains a header with an address of a source switch connected to an input port that receives the packet, and a destination switch connected to an output port that transmits the packet. Each packet header also contains a random address of a random switch in the network. The packet is first routed from the source switch toward the random switch. Then a phase flag in the header is cleared by the random switch, and the packet is routed toward the destination switch. If a faulty link or switch is encountered, and no known routes are available to the destination, the phase flag is again set and another random address generated. The packet is then routed to a new random switch, bypassing the fault.

摘要翻译： 互连网络在连接在多维链路网络中的交换机之间路由分组。 每个数据包包含一个标题，其头连接到接收数据包的输入端口的源交换机的地址，以及连接到发送数据包的输出端口的目标交换机。 每个分组报头还包含网络中随机交换机的随机地址。 数据包首先从源交换机路由到随机交换机。 然后标头中的相位标志由随机交换机清除，并且数据包被路由到目的地交换机。 如果遇到故障的链路或交换机，并且目的地没有已知的路由可用，则会重新设置相位标志，并生成另一个随机地址。 然后将数据包路由到新的随机交换机，绕过故障。