公开(公告)号：US20050206426A1

公开(公告)日：2005-09-22

申请号：US11134899

申请日：2005-05-23

申请人： Robert Proebsting ,  Cesar Talledo ,  David Pilling

发明人： Robert Proebsting ,  Cesar Talledo ,  David Pilling

IPC分类号： G11C7/00 ,  H03H11/26 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/081

CPC分类号： H03H11/265 ,  H03K3/0322 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00032 ,  H03K2005/00104 ,  H03K2005/00208 ,  H03K2005/00247 ,  H03K2005/00286 ,  H03L7/0812

摘要： An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.

摘要翻译： 集成电路延迟装置包括数字延迟线，其被配置为响应于控制信号向在其输入处接收的定时信号提供百分比时钟周期延迟。 该控制信号具有指定延迟长度的值。 还提供延迟线控制电路。 延迟线控制电路被配置为通过在具有大于时钟周期的持续时间的时间间隔内对具有小于时钟周期的周期的高频振荡器信号（例如，环形振荡器信号）的多个周期进行计数来生成控制信号 。

公开(公告)号：US06972596B1

公开(公告)日：2005-12-06

申请号：US10772106

申请日：2004-02-03

申请人： Robert Proebsting ,  Robert J. Bosnyak

发明人： Robert Proebsting ,  Robert J. Bosnyak

IPC分类号： H03K5/003 ,  H03K19/094

CPC分类号： H03K5/003 ,  H01L2225/06527

摘要： One embodiment of the present invention provides a system that amplifies capacitively coupled inter-chip communication signals. During operation, the system transmits a signal through a capacitive transmitter pad and receives a corresponding input signal through a capacitive receiver pad. The system amplifies the input signal by feeding it through a number of cascaded CMOS inverters operating from ever-increasing power supply voltages from the first to the last inverter. The system periodically initializes the input voltage of the first CMOS inverter by: suspending data transmission on the capacitive transmitter pad and setting the voltage on the capacitive transmitter pad to a middle point between a voltage that represents logic “1” and a voltage that represents logic “0”, coupling the output of the first CMOS inverter to its input through a switch, and, after the input voltage of the first CMOS inverter stage substantially stabilizes at the switching threshold, uncoupling the output of the first CMOS inverter stage from the input of the first CMOS inverter stage and then resuming data transmission on the capacitive transmitter pad.

摘要翻译： 本发明的一个实施例提供一种放大电容耦合芯片间通信信号的系统。 在操作期间，系统通过电容式发射器焊盘发送信号，并通过电容式接收器接收相应的输入信号。 该系统通过馈送多个级联的CMOS反相器来放大输入信号，这些反相器从第一个到最后一个逆变器的不断增加的电源电压工作。 系统通过以下方式周期性地初始化第一CMOS反相器的输入电压：将数据传输暂停在电容式发射器焊盘上，并将电容式发射器焊盘上的电压设置为表示逻辑“1”的电压与表示逻辑“1”的电压之间的中间点 “0”，通过开关将第一CMOS反相器的输出耦合到其输入，并且在第一CMOS反相器级的输入电压基本上稳定在开关阈值之后，将第一CMOS反相器级的输出与输入 的第一个CMOS反相器级，然后在电容式发射器焊盘上恢复数据传输。

公开(公告)号：US20050166009A1

公开(公告)日：2005-07-28

申请号：US11085770

申请日：2005-03-21

申请人： Robert Proebsting

发明人： Robert Proebsting

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4076 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G06F12/00

CPC分类号： G11C11/40618 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/104 ,  G11C2207/229 ,  H01L27/10891 ,  H01L27/10897

摘要： A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

摘要翻译： 动态随机存取存储器集成电路和方法包括内部刷新控制和被配置为接收具有优先于待处理刷新请求的优先级的读和写访问请求的阵列，其中刷新请求可排队并且在不需要阵列访问并且完成的时钟周期上退休 在一个时钟周期。 不需要板载高速缓存。 一种方法包括：当阵列中的一个阵列需要刷新时确定电路内的优先次序，优先考虑未决刷新请求的读取和写入访问请求，启动对阵列的访问的读取访问请求，而不确定数据是否可从数组外部获得 ，并且当该银行具有待处理的刷新请求并且不需要在该时钟周期上访问数组时，在一个时钟周期内退出一个等待刷新请求到银行。

公开(公告)号：US20050152199A1

公开(公告)日：2005-07-14

申请号：US10921760

申请日：2004-08-18

申请人： Kee Park ,  Robert Proebsting

发明人： Kee Park ,  Robert Proebsting

IPC分类号： G11C7/18 ,  G11C15/04 ,  G11C5/00

CPC分类号： G11C7/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097 ,  G11C15/043

摘要： A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to re-invert the inverted data values prior to being written to the 3T DRAM cells. In one embodiment, the 3T DRAM cells are cross-coupled to the bit lines, and the inverting refresh circuit transfers bits from one bit line to the other.

摘要翻译： 公开了一种CAM单元，其包括比较器和连接到一对相关位线的两个三晶体管（3T）DRAM单元。 使用每个3T DRAM单元的固有电容存储数据，并将其施加到比较器的下拉晶体管的栅极端子。 在刷新操作期间，将反相数据值写入位线，然后从位线写入3T DRAM单元。 在三元实施例中，反相刷新电路用于在被写入3T DRAM单元之前重新反转反相数据值。 在一个实施例中，3T DRAM单元被交叉耦合到位线，并且反相刷新电路将位从一个位线传输到另一位。

公开(公告)号：US08358155B2

公开(公告)日：2013-01-22

申请号：US12215943

申请日：2008-06-30

申请人： Alex Chow ,  Robert J. Drost ,  Ronald Ho ,  Arlene Proebsting

发明人： Alex Chow ,  Robert J. Drost ,  Ronald Ho ,  Robert Proebsting

IPC分类号： H03K19/20

CPC分类号： H01L23/48 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： One embodiment of the present invention provides a system that facilitates proximity communication. This system includes a circuit containing a bootstrap transistor and a pass-gate transistor, where the drain of the bootstrap transistor is coupled to the gate of the pass-gate transistor. Note that a first coupling capacitance exists between the source of the pass-gate transistor and the drain of the bootstrap transistor and a second coupling capacitance exists between the drain of the pass-gate transistor and the drain of the bootstrap transistor. During operation, the gate and the source of the bootstrap transistor are coupled to a high voltage, thereby causing an intermediate voltage at the drain of the bootstrap transistor. When the source of the pass-gate transistor transitions to a high voltage, the first coupling capacitance and the second coupling capacitance boost the voltage at the gate of the pass-gate transistor higher than the high voltage, thereby enabling the high voltage at the source of the pass-gate transistor to pass to the drain of the pass-gate transistor.