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    High capacity capacitor and corresponding manufacturing process
    11.
    发明授权
    High capacity capacitor and corresponding manufacturing process 失效
    大容量电容器及相应的制造工艺

    公开(公告)号：US06222245B1

    公开(公告)日：2001-04-24

    申请号：US08739997

    申请日：1996-10-30

    Applicant: Roberto Bez ,  Emilio Camerlenghi

    Inventor： Roberto Bez ,  Emilio Camerlenghi

    IPC: H01L2900

    CPC classification number: H01L28/40 ,  H01L29/94

    Abstract: The invention relates to a high-capacitance capacitor which is monolithically integratable on a semiconductor substrate doped with a first type of dopant and accommodating a diffusion well which is doped with a second type of dopant and has a first active region formed therein. A layer of gate oxide is deposited over the diffusion well which is covered with a first layer of polycrystalline silicon and separated from a second layer of polycrystalline silicon by an interpoly dielectric layer. Advantageously, the high-capacitance capacitor of the invention includes a first elementary capacitor having the first and second layers of polycrystalline silicon as its conductive plates, and the interpoly dielectric layer as the isolation dielectric, and a second elementary capacitor having the first layer of polycrystalline silicon and the diffusion well as its conductive plates and the gate oxide layer as the isolation dielectric.

    Abstract translation: 本发明涉及一种高容量电容器，该高容量电容器可单独集成在掺杂有第一类掺杂剂的半导体衬底上，并且容纳掺杂有第二类掺杂剂的扩散阱，并且其中形成有第一有源区。 栅极氧化物沉积在扩散阱上，该扩散阱被第一多晶硅层覆盖，并通过多晶硅介电层与第二多晶硅层分离。有利的是，本发明的大容量电容器包括具有 第一和第二层多晶硅作为其导电板，并且作为隔离电介质的多晶硅绝缘层，以及具有第一层多晶硅和扩散阱作为其导电板的第二基本电容器，以及作为隔离层的栅极氧化物层 电介质。

    Method for erasing an electrically programmable and erasable non-volatile memory cell
    12.
    发明授权
    Method for erasing an electrically programmable and erasable non-volatile memory cell 失效
    擦除电可编程和可擦除非易失性存储单元的方法

    公开(公告)号：US5784319A

    公开(公告)日：1998-07-21

    申请号：US788530

    申请日：1997-01-24

    Applicant: Corrado Villa ,  Roberto Bez ,  Daniele Cantarelli ,  Marco Dallabora

    Inventor： Corrado Villa ,  Roberto Bez ,  Daniele Cantarelli ,  Marco Dallabora

    IPC: G11C16/02 ,  G11C16/06 ,  G11C16/14

    CPC classification number: G11C16/14

    Abstract: A method for erasing an electrically programmable and erasable non-volatile memory cell having a control electrode, an electrically-insulated electrode and a first electrode. The method provides for coupling the control electrode to a first voltage supply and coupling the first electrode to a second voltage supply. The first voltage supply and the second voltage supply are suitable to cause tunneling of electric charges between the electrically-insulated electrode and the first electrode. The method also provides for a constant current to flow between the second voltage supply and the first electrode of the memory cell for at least part of an erasing time of the memory cell, the constant current having a prescribed value.

    Abstract translation: 一种用于擦除具有控制电极，电绝缘电极和第一电极的电可编程和可擦除非易失性存储单元的方法。 该方法提供将控制电极耦合到第一电压源并将第一电极耦合到第二电压源。 第一电压源和第二电压源适于在电绝缘电极和第一电极之间引起电荷的隧穿。 该方法还提供恒定电流在存储器单元的第二电压源和第一电极之间流动，用于存储单元的擦除时间的至少一部分，恒定电流具有规定值。

    Phase Change Memory Cells And Methods Of Forming Phase Change Memory Cells
    13.
    发明申请
    Phase Change Memory Cells And Methods Of Forming Phase Change Memory Cells 有权
    相变记忆细胞和形成相变记忆细胞的方法

    公开(公告)号：US20130285002A1

    公开(公告)日：2013-10-31

    申请号：US13460302

    申请日：2012-04-30

    Applicant: Damon E. Van Gerpen ,  Roberto Bez

    Inventor： Damon E. Van Gerpen ,  Roberto Bez

    IPC: H01L47/00 ,  H01L45/00

    CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

    Abstract: A phase change memory cell has first and second electrodes having phase change material there-between. The phase change memory cell is devoid of heater material as part of either of the first and second electrodes and being devoid of heater material between either of the first and second electrodes and the phase change material. A method of forming a memory cell having first and second electrodes having phase change material there-between includes lining elevationally inner sidewalls of an opening with conductive material to comprise the first electrode of the memory cell. Elevationally outer sidewalls of the opening are lined with dielectric material. Phase change material is formed in the opening laterally inward of and electrically coupled to the conductive material in the opening. Conductive second electrode material is formed that is electrically coupled to the phase change material. Other implementations are disclosed.

    Abstract translation: 相变存储单元具有在其间具有相变材料的第一和第二电极。 相变存储单元没有加热器材料作为第一和第二电极中的任一个的一部分，并且在第一和第二电极和相变材料中的任一个之间没有加热材料。 一种形成具有在其上具有相变材料的第一和第二电极的存储单元的方法包括：利用导电材料将具有导电材料的开口的正面内侧壁布置成包括存储单元的第一电极。 开口的高空外侧衬有介电材料。 相变材料形成在开口的横向内侧且与开口中的导电材料电耦合。 形成电耦合到相变材料的导电第二电极材料。 公开了其他实现。

    Process for manufacturing integrated resistive elements with silicidation protection
    14.
    发明授权
    Process for manufacturing integrated resistive elements with silicidation protection 有权
    具有硅化防护功能的集成电阻元件制造工艺

    公开(公告)号：US07566610B2

    公开(公告)日：2009-07-28

    申请号：US11343593

    申请日：2006-01-30

    Applicant: Alessandro Grossi ,  Roberto Bez ,  Giorgio Servalli

    Inventor： Alessandro Grossi ,  Roberto Bez ,  Giorgio Servalli

    IPC: H01L21/8234

    CPC classification number: H01L28/20 ,  H01L27/0802

    Abstract: In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a predetermined resistivity is then formed in the active area (15). Prior to forming the resistive region (21), however, a delimitation structure (20) for delimiting the resistive region (21) is obtained on top of the active area (15). Subsequently, protective elements (25) are obtained which extend within the delimitation structure (20) and coat the resistive region (21).

    Abstract translation: 在制造具有防止硅化物的集成电阻元件的工艺中，至少一个有源区域（15）在半导体晶片（10）中界定。 在有源区域（15）中形成具有预定电阻率的至少一个电阻区域（21）。 然而，在形成电阻区域（21）之前，在有源区域（15）的顶部获得用于限定电阻区域（21）的限定结构（20）。 随后，获得在限定结构（20）内延伸并涂覆电阻区（21）的保护元件（25）。

    Array of cells including a selection bipolar transistor and fabrication method thereof
    15.
    发明授权
    Array of cells including a selection bipolar transistor and fabrication method thereof 有权
    包括选择双极晶体管的单元阵列及其制造方法

    公开(公告)号：US07446011B2

    公开(公告)日：2008-11-04

    申请号：US11551170

    申请日：2006-10-19

    Applicant: Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

    Inventor： Fabio Pellizzer ,  Giulio Casagrande ,  Roberto Bez

    IPC: H01L21/8222

    CPC classification number: H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

    Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

    Abstract translation: 单元阵列由多个单元形成，每个单元包括选择双极晶体管和存储组件。 电池阵列形成在包括P型共用集电极区域的主体中; 多个N型基极区，覆盖在公共集电极区域上; 在基区中形成多个P型发射极区; 以及形成在所述基极区域中的多个N型基极接触区域和比所述基极区域更高的掺杂水平的基极接触区域，其中每个基极区域由至少两个相邻的双极晶体管共享。

    Field programmable gate array device
    17.
    发明授权
    Field programmable gate array device 有权
    现场可编程门阵列器件

    公开(公告)号：US07307451B2

    公开(公告)日：2007-12-11

    申请号：US10948079

    申请日：2004-09-23

    Applicant: Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    Inventor： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    IPC: H03K19/177 ,  G11C11/34

    CPC classification number: G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

    Abstract: The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    Abstract translation: 本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元 包括多个控制单元的布置。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值， 以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

    Phase change memory cell and manufacturing method thereof using minitrenches
    19.
    发明申请
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元及其制造方法

    公开(公告)号：US20050152208A1

    公开(公告)日：2005-07-14

    申请号：US11045170

    申请日：2005-01-27

    Applicant: Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    Inventor： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC: G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G01R31/08

    CPC classification number: H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    Abstract translation: 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

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