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11.发明申请Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry 失效自动驱动器/传输线/接收机阻抗匹配电路的设计结构公开(公告)号：US20090115448A1
公开(公告)日：2009-05-07
申请号：US11934825
申请日：2007-11-05
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03J3/185 , H03L7/08 , H03L7/0805 , H03L7/0891
摘要： A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
摘要翻译： 用于阻抗匹配器的设计结构，其自动匹配驱动器和接收器之间的阻抗。 阻抗匹配器的设计结构包括锁定到由驱动器提供的数据信号的锁相环（PLL）电路。 阻抗匹配器还包括响应于PLL电路内的一个或多个压控振荡器控制信号的可调阻抗匹配电路，以产生与接收器阻抗匹配的输出信号。
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12.发明授权Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of producing the same 有权具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元及其制造方法公开(公告)号：US06720602B2
公开(公告)日：2004-04-13
申请号：US10101992
申请日：2002-03-21
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译： 半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的 一对间隔字线导线。
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公开(公告)号：US06259126B1
公开(公告)日：2001-07-10
申请号：US09447628
申请日：1999-11-23
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , G11C11/005 , H01L27/105 , H01L27/1052 , H01L27/10852
摘要： A semiconductor memory device including at least three different types of memory cell structures. The types include an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate.
摘要翻译： 一种包括至少三种不同类型的存储单元结构的半导体存储器件。 这些类型包括NVRAM单元结构，FERAM单元结构，DRAM单元结构以及SRAM单元结构。 电池结构设置在相同的基板上。
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公开(公告)号：US07525170B2
公开(公告)日：2009-04-28
申请号：US11538557
申请日：2006-10-04
IPC分类号： H01L31/058
CPC分类号： H01L31/035281 , H01L27/1446 , H01L31/022408 , H01L31/022466 , H01L31/028 , H01L31/1804 , H01L31/1884 , Y02E10/547 , Y02P70/521
摘要： An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.
摘要翻译： 在半导体衬底上形成具有高纵横比的柱状p-i-n二极管的布置。 每个器件由位于柱的每个端部处的P +区域和N +区域之间的本征或轻掺杂区域（i区域）形成。 柱p-i-n二极管的布置被嵌入在光学透明介质中。 对于给定的表面积，p-i-n二极管的支柱排列比常规平面p-i-n二极管吸收更多的光能。 支柱p-i-n二极管优选地被配置成阵列形成，以使得从一个柱p-i-n二极管反射的光子被与第一个p-i-n二极管相邻的另一个p-i-n二极管捕获和吸收，从而优化了能量转换的效率。
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15.发明授权Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权具有不同晶体取向的共面绝缘体上硅（SOI）区域及其制造方法公开(公告)号：US07439108B2
公开(公告)日：2008-10-21
申请号：US11155030
申请日：2005-06-16
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了半导体器件制造的第一种方法。 第一种方法包括以下步骤：（1）提供衬底; 和（2）在基板上形成具有第一晶体取向的第一绝缘体上硅（SOI）区域，具有第二晶体取向的第二SOI区域和具有第三晶体取向的第三SOI区域。 第一，第二和第三SOI区域是共面的。 提供了许多其他方面。
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16.发明授权Design structure for an automatic driver/transmission line/receiver impedance matching circuitry 失效自动驱动/传输线路/接收机阻抗匹配电路的设计结构公开(公告)号：US07622946B2
公开(公告)日：2009-11-24
申请号：US11934825
申请日：2007-11-05
IPC分类号： H03K17/16 , H03K19/003 , H03L7/06
CPC分类号： H03K19/0005 , H03J3/185 , H03L7/08 , H03L7/0805 , H03L7/0891
摘要： A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.
摘要翻译： 用于阻抗匹配器的设计结构，其自动匹配驱动器和接收器之间的阻抗。 阻抗匹配器的设计结构包括锁定到由驱动器提供的数据信号的锁相环（PLL）电路。 阻抗匹配器还包括响应于PLL电路内的一个或多个压控振荡器控制信号的可调阻抗匹配电路，以便产生与接收器阻抗匹配的输出信号。
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17.发明授权Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor 失效具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元的制造方法公开(公告)号：US06399447B1
公开(公告)日：2002-06-04
申请号：US09619671
申请日：2000-07-19
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译： 半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的 一对间隔字线导线。
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18.发明授权
公开(公告)号：US6141242A
公开(公告)日：2000-10-31
申请号：US447629
申请日：1999-11-23
IPC分类号： G11C11/00 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/10894 , G11C11/005 , H01L27/105 , H01L27/10808 , H01L27/115 , H01L27/11517 , H01L27/11526 , H01L27/10852
摘要： A semiconductor memory device including at least three of the following cell structures: an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate and preferably have gate surfaces which are substantially coplanar. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, FERAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.
摘要翻译： 包括以下单元结构中的至少三个的半导体存储器件：NVRAM单元结构，FERAM单元结构，DRAM单元结构和SRAM单元结构。 电池结构设置在相同的衬底上，并且优选地具有基本共面的栅极表面。 NVRAM单元结构。 用于形成在一个衬底上包括NVRAM，FERAM，DRAM和/或SRAM存储器结构的存储器结构的处理，以及用于形成新的NVRAM单元结构的处理。
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19.发明授权Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权具有不同晶体取向的共面绝缘体上硅（SOI）区域及其制造方法公开(公告)号：US07525121B2
公开(公告)日：2009-04-28
申请号：US11929490
申请日：2007-10-30
IPC分类号： H01L29/10 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了半导体器件制造的第一种方法。 第一种方法包括以下步骤：（1）提供衬底; 和（2）在基板上形成具有第一晶体取向的第一绝缘体上硅（SOI）区域，具有第二晶体取向的第二SOI区域和具有第三晶体取向的第三SOI区域。 第一，第二和第三SOI区域是共面的。 提供了许多其他方面。
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公开(公告)号：US20080083963A1
公开(公告)日：2008-04-10
申请号：US11538557
申请日：2006-10-04
IPC分类号： H01L27/14
CPC分类号： H01L31/035281 , H01L27/1446 , H01L31/022408 , H01L31/022466 , H01L31/028 , H01L31/1804 , H01L31/1884 , Y02E10/547 , Y02P70/521
摘要： An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The p-i-n diodes are configured in an array formation to enable photons reflected from one p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of the energy conversion.
摘要翻译： 在半导体衬底上形成具有高纵横比的柱状p-i-n二极管的布置。 每个器件由位于柱的每个端部处的P +区域和N +区域之间的本征或轻掺杂区域（i区域）形成。 p-i-n二极管的布置被嵌入在光学透明介质中。 对于给定的表面积，p-i-n二极管的支柱排列比常规平面p-i-n二极管吸收更多的光能。 p-i-n二极管被配置成阵列形成以使得从一个p-i-n二极管反射的光子能够被与第一个p-i-n二极管相邻的另一个p-i-n二极管捕获和吸收，从而优化了能量转换的效率。
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