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1.发明授权Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of producing the same 有权具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元及其制造方法公开(公告)号：US06720602B2
公开(公告)日：2004-04-13
申请号：US10101992
申请日：2002-03-21
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译： 半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的 一对间隔字线导线。
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公开(公告)号：US06632741B1
公开(公告)日：2003-10-14
申请号：US09619664
申请日：2000-07-19
IPC分类号： H01L21302
CPC分类号： H01L21/0334
摘要： A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material along the sidewalls of the features in the first material.
摘要翻译： 一种自修剪图案的方法包括在沉积在基底上的第一材料中形成包含多个规则或不规则特征的图案，沉积第二材料的共形层，并蚀刻第二材料以形成第二材料的间隔物 第一种材料的特征侧壁。
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3.发明授权Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor 失效具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元的制造方法公开(公告)号：US06399447B1
公开(公告)日：2002-06-04
申请号：US09619671
申请日：2000-07-19
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译： 半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的 一对间隔字线导线。
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4.发明授权N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same 失效N沟道金属氧化物半导体（NMOS）驱动电路及其制造方法公开(公告)号：US06964892B2
公开(公告)日：2005-11-15
申请号：US10155731
申请日：2002-05-28
IPC分类号： H01L23/522 , H01L21/225 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/8238 , H01L21/00 , H01L21/84
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/76895 , H01L27/088 , Y10S438/969
摘要： An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack.
摘要翻译： N沟道金属氧化物半导体（NMOS）驱动电路（及其制造方法）包括形成在衬底上并具有通过低浓度注入形成的源极和漏极的升压栅极堆叠以及耦合到 升压栅极堆叠。
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5.发明授权N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same 失效N沟道金属氧化物半导体（NMOS）驱动电路及其制造方法公开(公告)号：US06433397B1
公开(公告)日：2002-08-13
申请号：US09488515
申请日：2000-01-21
IPC分类号： H01L27085
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/76895 , H01L27/088 , Y10S438/969
摘要： An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.
摘要翻译： N沟道金属氧化物半导体（NMOS）驱动电路（及其制造方法）包括形成在基板上的升压栅叠层，具有通过低浓度N型注入形成的源极和漏极，以及N- 驱动器耦合到升压栅极堆叠。
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公开(公告)号：US06426903B1
公开(公告)日：2002-07-30
申请号：US09923721
申请日：2001-08-07
IPC分类号： G11C700
CPC分类号： G11C29/80 , Y10S977/888 , Y10S977/943
摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.
摘要翻译： 使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。 聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。 反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。
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公开(公告)号：US07714452B2
公开(公告)日：2010-05-11
申请号：US11847776
申请日：2007-08-30
申请人： Lawrence A. Clevenger , Mukta Ghate Farooq , Louis Lu-Chen Hsu , William Francis Landers , Donna S. Zupanski-Nielson , Carl John Radens , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Mukta Ghate Farooq , Louis Lu-Chen Hsu , William Francis Landers , Donna S. Zupanski-Nielson , Carl John Radens , Chih-Chao Yang
CPC分类号： H05K3/3436 , H01L23/13 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/11 , H01L24/12 , H01L24/17 , H01L24/49 , H01L24/73 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/06102 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/49109 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , Y02P70/613 , H01L2224/29099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.
摘要翻译： 一种电结构和方法，包括电和机械地连接到第二衬底的第一衬底。 第一基板包括第一导电焊盘和第二导电焊盘。 第二基板包括第三导电焊盘，第四导电焊盘和第一导电部件。 第四导电焊盘包括与第一导电构件的高度不同的高度。 导电构件电连接和机械地连接到第四导电垫。 第一焊球将第一导电焊盘连接到第三导电焊盘。 第一焊球包括第一直径。 第二焊球将第二导电焊盘连接到第一导电构件。 第二焊球包括第二直径。 第一直径大于所述第二直径。
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公开(公告)号：US06495445B2
公开(公告)日：2002-12-17
申请号：US09825653
申请日：2001-04-04
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , G06Q10/0639 , G06Q40/04
摘要： Disclosed is a structure and process for incorporating air or other gas as a permanent dielectric medium in a multilevel chip by providing CVD diamond as a semi-sacrificial interlevel and intralevel dielectric material. The semi-sacrificial dielectric is subsequently at least partially removed in an isotropic oxygen etch. A variation of the disclosure includes providing a final, permanent CVD diamond encapsulant to contain the gaseous dielectric medium within the chip.
摘要翻译： 公开了一种通过提供CVD金刚石作为半牺牲层间和体内电介质材料将空气或其它气体作为永久介电介质并入多层芯片的结构和方法。 随后在各向同性氧蚀刻中至少部分去除半牺牲电介质。 本公开的变体包括提供最终的永久CVD金刚石密封剂以容纳芯片内的气态电介质。
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公开(公告)号：US20090212341A1
公开(公告)日：2009-08-27
申请号：US12034899
申请日：2008-02-21
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译： 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。
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公开(公告)号：US07868374B2
公开(公告)日：2011-01-11
申请号：US12034899
申请日：2008-02-21
IPC分类号： H01L29/788
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/10826 , H01L29/66795 , H01L29/7841 , H01L29/7853
摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.
摘要翻译： 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。
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