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    LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES
    11.
    发明申请
    LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES 有权
    布线确定宽线芯片互连线

    公开(公告)号：US20110179392A1

    公开(公告)日：2011-07-21

    申请号：US13069411

    申请日：2011-03-23

    申请人： Rachel Gordin ,  David Goren ,  Sue Ellen Strang ,  Kurt Alan Tallman ,  Youri V. Tretiakov

    发明人： Rachel Gordin ,  David Goren ,  Sue Ellen Strang ,  Kurt Alan Tallman ,  Youri V. Tretiakov

    IPC分类号： G06F17/50

    CPC分类号： H01L23/528 ,  H01L21/7684 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

    摘要翻译： 提供了一种用于确定互连线的布局的方法，包括：为所述互连线提供所需的宽度; 确定所述互连线的布局，包括切开所述互连线以提供沿着所述互连线延伸的两个或更多个手指，所述两个或更多个指状物与分隔相邻手指的细长狭槽; 以及通过将所需宽度与固体金属特征的最大宽度进行比较，以及最小的细长孔宽度来确定要布置在互连线的宽度上的多个细长孔。 两个或更多个手指和细长槽可以具有恒定的宽度并且跨越互连线宽度等间隔。 该方法可以包括选择手指的数量和槽的宽度以优化给定层技术的布局。

    CAPACITANCE MODELING
    13.
    发明申请
    CAPACITANCE MODELING 有权
    电容建模

    公开(公告)号：US20080244485A1

    公开(公告)日：2008-10-02

    申请号：US12137277

    申请日：2008-06-11

    申请人： Rachel Gordin ,  David Goren

    发明人： Rachel Gordin ,  David Goren

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-clip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (∈1) and the substrate is a second dielectric with a second permittivity (∈2). The method models the capacitance (C1) for values of the first and second permittivity (∈1, ∈2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (∈1) and a different second permittivity (∈2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

    摘要翻译： 一种用于结构建模的方法，该结构包括由电介质材料包围并由衬底支撑的一对长导体。 特别地，该结构可以是在以非常高的频率操作的导电衬底上的夹具共面传输线，使得衬底表现为完美的电介质。 假设周围的电介质材料是具有第一介电常数（εε1）的第一电介质，并且衬底是具有第二介电常数（ε2 2 N 2）的第二电介质。 该方法基于已知的电容（第一和第二介电常数（∈1 SUB，∈2））的值来模拟电容（C 1> 对于具有相同的第一介电常数（εε1 1）的基础结构和不同的第二介电常数（ε2 2 N）计算出的数学公式（C 2＆lt; 2＆gt; 2）。 建议外推或内插公式，以通过一个或多个已知电容（C 2> 2）来建模所寻找的电容（C 1> 1）。

    Device and method for reducing dishing of critical on-chip interconnect lines
    14.
    发明申请
    Device and method for reducing dishing of critical on-chip interconnect lines 审中-公开
    减少关键片上互连线的凹陷的装置和方法

    公开(公告)号：US20060072257A1

    公开(公告)日：2006-04-06

    申请号：US10954672

    申请日：2004-09-30

    申请人： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

    发明人： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

    IPC分类号： H02H9/00

    CPC分类号： H01L23/528 ,  H01L21/7684 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An critical interconnect line (300) for an integrated circuit is provided in which the problem of dishing of copper is addressed. An interconnect line (300) is provided for an integrated circuit in the form of a critical interconnect line modelled as a transmission line. The interconnect line (300) is formed of a conductive material having a width (302) and a length (303). The interconnect line (300) comprises at least two fingers (304, 305, 306) extending the length (303) of the interconnect line (300), an elongate aperture (309) in the conductive material separating two adjacent fingers (304, 305, 306), and one or more bridges (308) joining the fingers (304, 305, 306) at intervals along the length (303) of the interconnect line (300). The fingers (303, 304, 305) are kept within a width for which the effect of dishing acceptable width whilst the bridges (307, 308) keep the fingers (304, 305, 306) at the same potential difference.

    摘要翻译： 提供了一种用于集成电路的关键互连线（300），其中解决了铜的凹陷问题。 为以建模为传输线的关键互连线的形式的集成电路提供互连线（300）。 互连线（300）由具有宽度（302）和长度（303）的导电材料形成。 互连线（300）包括延伸互连线（300）的长度（303）的至少两个指状物（304,305,306），导电材料中的细长孔（309），分隔两个相邻的指状物（304,305 ，306）和沿着所述互连线（300）的长度（303）的间隔连接所述指状物（304,305,306）的一个或多个桥接器（308）。 手指（303,304,305）保持在一个宽度内，当桥接器（307,308）将手指（304,305,306）保持在相同的电位差时，凹槽可接受宽度的影响。

    Interconnect-aware integrated circuit design
    15.
    发明申请
    Interconnect-aware integrated circuit design 失效
    互连式集成电路设计

    公开(公告)号：US20050114819A1

    公开(公告)日：2005-05-26

    申请号：US10723752

    申请日：2003-11-26

    申请人： David Goren ,  Rachel Gordin ,  Michael Zelikson

    发明人： David Goren ,  Rachel Gordin ,  Michael Zelikson

    IPC分类号： G06F17/50 ,  G06F9/455 ,  H01L21/82

    CPC分类号： G06F17/5036

    摘要： In a system 10 for designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line model 35 is defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line model 35 for each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line model 35 representing a critical interconnect line affected by a crossing line, an environment terminal 36 is provided. The environment terminal 36 comprises a connection to the model 35 via at least one circuit component representing the effect of the crossing line on the model. The environment terminal 36 is connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.

    摘要翻译： 在用于设计集成电路的系统10中，定义了集成电路的初步设计，并且识别了初步设计中的关键互连线。 此外，识别在初步设计中受交叉线影响的任何关键互连线，并且传输线模型35被定义为表示每个关键互连线。 然后使用用于每个关键互连线的初步设计和传输线模型35来定义包括电路部件及其参数的集成电路的布局设计。 然后从布局设计中提取组件参数，以使用提取的组件参数进行设计的仿真。 在该设计过程中，对于表示受交叉线影响的关键互连线的每个传输线模型35，提供环境终端36。 环境终端36包括通过表示模型上的交叉线的影响的至少一个电路组件到模型35的连接。 环境端子36在集成电路设计中连接到适当的交叉线，由此在设计过程中容纳交叉线效应。

    Layout determining for wide wire on-chip interconnect lines
    16.
    发明授权
    Layout determining for wide wire on-chip interconnect lines 有权
    广泛的线内互连线路的布局确定

    公开(公告)号：US08943456B2

    公开(公告)日：2015-01-27

    申请号：US13069411

    申请日：2011-03-23

    申请人： Rachel Gordin ,  David Goren ,  Sue Ellen Strang ,  Kurt Alan Tallman ,  Youri V. Tretiakov

    发明人： Rachel Gordin ,  David Goren ,  Sue Ellen Strang ,  Kurt Alan Tallman ,  Youri V. Tretiakov

    IPC分类号： G06F17/50 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L23/528 ,  H01L21/7684 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

    摘要翻译： 提供了一种用于确定互连线的布局的方法，包括：为所述互连线提供所需的宽度; 确定所述互连线的布局，包括切开所述互连线以提供沿着所述互连线延伸的两个或更多个手指，所述两个或更多个指状物与分隔相邻手指的细长狭槽; 以及通过将所需宽度与固体金属特征的最大宽度进行比较，以及最小的细长孔宽度来确定要布置在互连线的宽度上的多个细长孔。 两个或更多个手指和细长槽可以具有恒定的宽度并且跨越互连线宽度等间隔。 该方法可以包括选择手指的数量和槽的宽度以优化给定层技术的布局。

    Topologies and methodologies for AMS integrated circuit design
    17.
    发明授权
    Topologies and methodologies for AMS integrated circuit design 有权
    AMS集成电路设计的拓扑和方法

    公开(公告)号：US08347244B2

    公开(公告)日：2013-01-01

    申请号：US11927720

    申请日：2007-12-11

    申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Sherman Anatoly ,  Michael Zelikson

    发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Sherman Anatoly ,  Michael Zelikson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  G06F2217/86

    摘要： A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

    摘要翻译： 用于模拟和混合信号电路的工具包括使得用户能够识别芯片架构中的一个或多个关键互连线和用于所述关键互连线的一个或多个可选择的预定义拓扑的单元。 每个拓扑包括一个或多个信号线和电流返回路径。 大部分电场线包含在拓扑的边界内。 本发明还包括一种用于设计模拟和混合信号（AMS）集成电路（IC）的方法，包括定义芯片架构和平面图，识别一个或多个关键互连线，并为关键互连选择预先设计的传输线拓扑 线条。

    Topologies and Methodologies for AMS Integrated Circuit Design
    18.
    发明申请
    Topologies and Methodologies for AMS Integrated Circuit Design 有权
    AMS集成电路设计的拓扑和方法

    公开(公告)号：US20090150848A1

    公开(公告)日：2009-06-11

    申请号：US11927720

    申请日：2007-12-11

    申请人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

    发明人： Amir Alon ,  David Goren ,  Rachel Gordin ,  Betty Livshitz ,  Anatoly Sherman ,  Michael Zelikson

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  G06F2217/86

    摘要： A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

    摘要翻译： 用于模拟和混合信号电路的工具包括使得用户能够识别芯片架构中的一个或多个关键互连线和用于所述关键互连线的一个或多个可选择的预定义拓扑的单元。 每个拓扑包括一个或多个信号线和电流返回路径。 大部分电场线包含在拓扑的边界内。 本发明还包括一种用于设计模拟和混合信号（AMS）集成电路（IC）的方法，包括定义芯片架构和平面图，识别一个或多个关键互连线并且为关键互连选择预先设计的传输线拓扑 线条。

    Coil inductor for on-chip or on-chip stack
    19.
    发明授权
    Coil inductor for on-chip or on-chip stack 有权
    用于片上或片上堆叠的线圈电感

    公开(公告)号：US09105627B2

    公开(公告)日：2015-08-11

    申请号：US13289071

    申请日：2011-11-04

    申请人： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    发明人： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    IPC分类号： H01F5/00 ,  H01L27/08 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/00

    CPC分类号： H01L23/49822 ,  H01F17/0013 ,  H01F41/005 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

    摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

    摘要翻译： 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。