Coil inductor for on-chip or on-chip stack
    1.
    发明授权
    Coil inductor for on-chip or on-chip stack 有权
    用于片上或片上堆叠的线圈电感

    公开(公告)号:US09105627B2

    公开(公告)日:2015-08-11

    申请号:US13289071

    申请日:2011-11-04

    摘要: A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

    摘要翻译: 提供了一种结合线圈电感器的线圈电感器和降压稳压器,其可以制造在诸如半导体芯片的微电子元件上,或者在诸如半导体,玻璃或陶瓷插入元件的互连元件上。 当通电时,线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量,并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中,线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成,沿着微电子或互连元件的第二表面延伸的第二导电线,以及多个导电通孔, 通过硅通孔,在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。

    Stacked Through-Silicon Via (TSV) Transformer Structure
    3.
    发明申请
    Stacked Through-Silicon Via (TSV) Transformer Structure 有权
    堆叠通硅(TSV)变压器结构

    公开(公告)号:US20130307656A1

    公开(公告)日:2013-11-21

    申请号:US13474239

    申请日:2012-05-17

    IPC分类号: H01F27/40 H01F7/06 H01F27/28

    摘要: A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.

    摘要翻译: 提供一种分布式有源变压器,其包括初级和次级绕组。 初级绕组包括在元件的第一表面和第二表面之间的方向上延伸的第一组导电通孔,沿着第一表面延伸的第一组第一导电线,以及延伸的第一组第二导电线 沿着第二个表面。 次级绕组包括在第一表面和第二表面之间的方向上延伸的第二组导电通孔,沿着第一表面延伸的第二组第一导电线,以及沿着第二表面延伸的第二组第二导电线 表面。 当通电时,初级绕组产生沿平行于第一表面和第二表面的方向延伸的磁通量。 次级绕组接收由初级绕组产生的磁通传递的能量。

    Circuit timing monitor having a selectable-path ring oscillator
    4.
    发明授权
    Circuit timing monitor having a selectable-path ring oscillator 失效
    具有可选路径环形振荡器的电路定时监视器

    公开(公告)号:US07810000B2

    公开(公告)日:2010-10-05

    申请号:US11559436

    申请日:2006-11-14

    IPC分类号: G01R31/3181 G01R31/30

    摘要: An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.

    摘要翻译: 具有可选路径环形振荡器电路的在线定时监视器在实际电路环境中提供延迟和性能测量。 测试模式信号被施加到数字电路以取消选择施加到数字电路内的功能逻辑块的给定功能输入信号,并且当选择测试模式操作时,将其与从功能逻辑块的输出耦合的反馈替换 。 选择从选择输入到输出的信号路径,使得信号路径振荡,并且测量输出信号的特征频率或相位以确定延迟。 将功能逻辑块的其他输入设置为预定的一组逻辑值。 可以在数字输入之前的寄存器处进行选择,或者在功能逻辑块的逻辑的第一级中进行选择。

    Digital duty cycle corrector
    5.
    发明授权
    Digital duty cycle corrector 失效
    数字占空比校正器

    公开(公告)号:US07667513B2

    公开(公告)日:2010-02-23

    申请号:US10988454

    申请日:2004-11-12

    IPC分类号: H03K3/017

    CPC分类号: H03K5/1565

    摘要: A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.

    摘要翻译: 公开了一种校正数字信号占空比的电路和方法。 测量输入数字信号的占空比并将其与期望的占空比进行比较。 输入数字信号的前沿被传递到输出。 该电路和方法调节输出端的下降沿以达到所需的占空比。 响应于延迟版本的输入数字信号的上升沿发生下降沿。

    CIRCULAR EDGE DETECTOR
    6.
    发明申请
    CIRCULAR EDGE DETECTOR 失效
    圆形边缘检测器

    公开(公告)号:US20100102854A1

    公开(公告)日:2010-04-29

    申请号:US12621763

    申请日:2009-11-19

    IPC分类号: H03K5/22

    CPC分类号: H03K5/1534

    摘要: A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

    摘要翻译: 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器,所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块,以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个,作为用于下一个边缘检测器单元的先前单元信号,并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

    Circular Edge Detector
    7.
    发明申请
    Circular Edge Detector 失效
    圆形边缘检测器

    公开(公告)号:US20080122490A1

    公开(公告)日:2008-05-29

    申请号:US11563888

    申请日:2006-11-28

    IPC分类号: H03K5/22

    CPC分类号: H03K5/1534

    摘要: A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

    摘要翻译: 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器,所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块,以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个,作为用于下一个边缘检测器单元的先前单元信号,并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。

    CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION
    9.
    发明申请
    CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION 有权
    具有选择性操作模式和单边缘检测的关键路径监视器

    公开(公告)号:US20120043982A1

    公开(公告)日:2012-02-23

    申请号:US12861289

    申请日:2010-08-23

    IPC分类号: G01R31/3187

    CPC分类号: G01R31/31725

    摘要: A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.

    摘要翻译: 具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。 脉冲通过表示功能逻辑电路中的关键路径的合成路径传播,合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。 测量的延迟被提供为实时输出,并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果,从而提供描述关于关键路径延迟的实时数据的不同信息,例如 作为对应于关键路径延迟的变化的边缘位置的范围。

    Circular edge detector for measuring timing of data signals
    10.
    发明授权
    Circular edge detector for measuring timing of data signals 失效
    用于测量数据信号定时的圆形边缘检测器

    公开(公告)号:US07759980B2

    公开(公告)日:2010-07-20

    申请号:US11563888

    申请日:2006-11-28

    IPC分类号: H03K5/22

    CPC分类号: H03K5/1534

    摘要: A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

    摘要翻译: 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器,所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块,以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个,作为用于下一个边缘检测器单元的先前单元信号,并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。