公开(公告)号：US20220066328A1

公开(公告)日：2022-03-03

申请号：US17234908

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soon Hwan CHA ,  Chan HWANG ,  Woo Jin JUNG

IPC: G03F7/20

Abstract: A semiconductor device manufacturing system includes a photolithography apparatus that performs exposure. On a semiconductor substrate including a chip area and a scribe lane area. An etching apparatus etches the exposed semiconductor substrate. An observing apparatus images the etched semiconductor substrate. A controller controls the photolithography apparatus and the etching apparatus. The controller generates a first mask pattern and provides the first mask pattern to the photolithography apparatus. The photolithography apparatus performs exposure on the semiconductor substrate using the first mask pattern. The etching apparatus performs etching on the exposed semiconductor substrate to provide an etched semiconductor substrate. The observing apparatus generates a first semiconductor substrate image by imaging the etched semiconductor substrate corresponding to the scribe lane area. The controller generates a second mask pattern based on the first mask pattern and the first semiconductor substrate image, and provides the second mask pattern to the photolithography apparatus.

公开(公告)号：US20200152638A1

公开(公告)日：2020-05-14

申请号：US16745956

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon-mok HA ,  Jae-hee KIM ,  Chan HWANG ,  Jong-hyuk KIM

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/311

Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.

公开(公告)号：US20170261317A1

公开(公告)日：2017-09-14

申请号：US15448325

申请日：2017-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon LEE ,  Chan HWANG ,  Jeong Jin LEE

IPC: G01B11/27 ,  G01B11/00

CPC classification number: G01B11/272 ,  G01B11/002 ,  G03F9/7084 ,  H01L2224/16145

Abstract: A method for measuring wafer alignment is provided. The method includes providing a plurality of first mark patterns extending in a first direction on a wafer, providing at least one second mark pattern on the first mark patterns such that it overlaps and intersects the first mark patterns, irradiating an optical signal onto the first mark patterns and the second mark pattern and obtaining coordinates of the second mark pattern by detecting signals from the second mark pattern.

公开(公告)号：US20250147409A1

公开(公告)日：2025-05-08

申请号：US18773908

申请日：2024-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo-Yong JUNG ,  Joon Hyun KIM ,  Seung Yoon LEE ,  Jeong Jin LEE ,  Chan HWANG

IPC: G03F1/42

Abstract: A method for manufacturing a semiconductor device includes providing a first pre-reticle including a first overlay mark and a first on-cell pattern. A second pre-reticle is provided that includes a second overlay mark and a second on-cell pattern. A first pattern is formed from the first pre-reticle using a first illumination system. A second pattern is formed from the second pre-reticle using a second illumination system. An overlay error is measured between the first pattern and the second pattern. A corrected reticle is formed based on the measured overlay error.

公开(公告)号：US20240258178A1

公开(公告)日：2024-08-01

申请号：US18396878

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu LEE ,  Minsu KANG ,  Sangho YUN ,  Chan HWANG

IPC: H01L21/66

CPC classification number: H01L22/12

Abstract: A method of detecting overlay of patterns includes forming a lower pattern and an upper pattern on a substrate. A sample pattern is drawn that has a common tangential line with the lower pattern. A position of a real center of gravity of the lower pattern is calculated using the common tangential line.

公开(公告)号：US20210397079A1

公开(公告)日：2021-12-23

申请号：US17464826

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doogyu LEE ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG

IPC: G03F1/24 ,  G03F7/20 ,  H01L21/027

Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

公开(公告)号：US20200209733A1

公开(公告)日：2020-07-02

申请号：US16815219

申请日：2020-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-hee KIM ,  Chan HWANG

IPC: G03F1/26 ,  G03F1/36 ,  H01L21/283 ,  H01L21/311 ,  H01L29/41 ,  G03F1/32

Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

公开(公告)号：US20180341172A1

公开(公告)日：2018-11-29

申请号：US15865636

申请日：2018-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-hee KIM ,  Chan HWANG

IPC: G03F1/26 ,  G03F1/36 ,  H01L29/41 ,  H01L21/311 ,  H01L21/283

Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

公开(公告)号：US20240234332A1

公开(公告)日：2024-07-11

申请号：US18489354

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junseok PARK ,  Seunghak PARK ,  Chan HWANG

IPC: H01L23/544 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/27 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device includes a first stack structure in a first region, a first channel structure in contact with the substrate, a second stack structure on the first stack structure, a second channel structure connected to the first channel structure, a third stack structure on the second stack structure, a third channel structure connected to the second channel structure, a first mold structure in a second region, first overlay structures on the first mold structure, a second mold structure on the first mold structure, second overlay structures on the second mold structure, a third mold structure on the second mold structure, and third overlay structures on the third mold structure, wherein the first to third overlay structures are on an overlay mark region, and the first to third overlay structures are in at least one of quadrants in the overlay mark region.

公开(公告)号：US20240152046A1

公开(公告)日：2024-05-09

申请号：US18218246

申请日：2023-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongjin LEE ,  Doogyu LEE ,  Seungyoon LEE ,  Chan HWANG

IPC: G03F1/70 ,  G03F7/00 ,  G03F7/20

CPC classification number: G03F1/70 ,  G03F7/2004 ,  G03F7/70033 ,  G03F7/70558

Abstract: A method of controlling semiconductor process includes forming a plurality of sample overlay keys by irradiating a first dose of extreme ultraviolet (EUV) light to a first photoresist layer formed on at least one sample wafer; determining a sample correction parameter for correcting a sample overlay error measured from the plurality of sample overlay keys; updating the sample correction parameter based on a difference between the first dose and a second dose; forming a plurality of main overlay keys by irradiating a second dose of extreme ultraviolet light to a second photoresist layer formed on the sample wafer based on the updated sample correction parameter; determining the main correction parameter based on a main overlay error measured from the plurality of main overlay keys; and performing a photolithography process on a wafer different from the sample wafer based on the main correction parameter.