AMPLIFIER
    12.
    发明申请

    公开(公告)号:US20210036672A1

    公开(公告)日:2021-02-04

    申请号:US16791728

    申请日:2020-02-14

    Abstract: An amplifier includes: a first input transistor connected to a first input, a first output, and a power source or a ground, a second input transistor connected to a second input, a second output, and the power source or the ground; a first replica transistor connected to the first input, a detection node, and the power source or the ground; a second replica transistor connected to the second input, the detection node, and the power source or the ground; and a bias transistor connected to a bias voltage, the detection node, and the power source or the ground.

    NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION

    公开(公告)号:US20200074286A1

    公开(公告)日:2020-03-05

    申请号:US16556424

    申请日:2019-08-30

    Abstract: A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.

    TWO-DIMENSIONAL ARRAY-BASED NEUROMORPHIC PROCESSOR AND IMPLEMENTING METHOD

    公开(公告)号:US20230214637A1

    公开(公告)日:2023-07-06

    申请号:US18120137

    申请日:2023-03-10

    CPC classification number: G06N3/063 G06F7/523 G06F7/50 G06F2207/4824

    Abstract: A 2D array-based neuromorphic processor includes: axon circuits each being configured to receive a first input corresponding to one bit from among bits indicating n-bit activation; first direction lines extending in a first direction from the axon circuits; second direction lines intersecting the first direction lines; synapse circuits disposed at intersections of the first direction lines and the second direction lines, and each being configured to store a second input corresponding to one bit from among bits indicating an m-bit weight and to output operation values of the first input and the second input; and neuron circuits connected to the first or second direction lines, each of the neuron circuits being configured to receive an operation value output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and to perform an arithmetic operation by using the operation values.

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