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公开(公告)号：US11201069B2
公开(公告)日：2021-12-14
申请号：US16995093
申请日：2020-08-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Ick Son , Dae Seok Byeon , Bong Soon Lim
IPC: H01L21/67 , H01L21/66 , H01L23/00 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L27/11573 , G11C8/14 , G11C7/18 , H01L25/18
Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.
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公开(公告)号：US11195587B2
公开(公告)日：2021-12-07
申请号：US16886053
申请日：2020-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Ick Son , Dae Seok Byeon , Bong Soon Lim
Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.
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公开(公告)号：US20190252027A1
公开(公告)日：2019-08-15
申请号：US16141294
申请日：2018-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
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Patent Agency Ranking
公开(公告)号：US11950425B2
公开(公告)日：2024-04-02
申请号：US17313649
申请日：2021-05-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myung Hun Lee , Dong Ha Shin , Pan Suk Kwak , Dae Seok Byeon
CPC classification number: H10B43/50 , H01L23/535 , H10B41/27 , H10B41/41 , H10B41/50 , H10B43/27 , H10B43/40
Abstract: A mold structure includes gate electrodes stacked on a first substrate, a channel structure penetrating a first region of the mold structure to cross the gate electrodes, a first through structure penetrating a second region of the mold structure, and a second through structure penetrating a third region of the mold structure. The mold structure includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell and dummy blocks includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.
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15.发明授权公开(公告)号：US11854627B2
公开(公告)日：2023-12-26
申请号：US17675085
申请日：2022-02-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
CPC classification number: G11C16/26 , G11C5/147 , G11C11/5642 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/32 , G11C2211/5642
Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.
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16.发明授权公开(公告)号：US11295818B2
公开(公告)日：2022-04-05
申请号：US17029265
申请日：2020-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.
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公开(公告)号：US11183251B2
公开(公告)日：2021-11-23
申请号：US17168613
申请日：2021-02-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
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公开(公告)号：US10559362B2
公开(公告)日：2020-02-11
申请号：US16141294
申请日：2018-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong Jin Shin , Ji Su Kim , Dae Seok Byeon , Ji Sang Lee , Jun Jin Kong , Eun Chu Oh
Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
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