公开(公告)号：US12237250B2

公开(公告)日：2025-02-25

申请号：US17498893

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Minjung Kim ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

公开(公告)号：US20230056041A1

公开(公告)日：2023-02-23

申请号：US17706978

申请日：2022-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Jongyoun Kim ,  Seokhyun Lee ,  Minjung Kim

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a base substrate including a lower redistribution layer; a lower semiconductor chip including a first active surface and on the base substrate; an upper semiconductor chip including a second active surface on the lower semiconductor chip and having an area larger than that of the lower semiconductor chip; an intermediate connection member including an upper redistribution layer on the second active surface of the upper semiconductor chip between the lower and upper semiconductor chips; a plurality of vertical interconnectors disposed around the lower semiconductor chip on the base substrate and connecting the lower redistribution layer and the upper redistribution layer; and a molding portion on the base substrate and including a first portion surrounding the lower semiconductor chip and the vertical interconnectors, and a second portion extending upwardly from the first portion and on side surfaces of the upper semiconductor chip and the intermediate connection member.

公开(公告)号：US20230019311A1

公开(公告)日：2023-01-19

申请号：US17731416

申请日：2022-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  Dongkyu Kim ,  Jongyoun Kim ,  Hyeonjeong Hwang

IPC: H01L23/498 ,  H01L25/10

Abstract: A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

公开(公告)号：US20220077048A1

公开(公告)日：2022-03-10

申请号：US17329256

申请日：2021-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Keung Beum Kim ,  Dongkyu Kim ,  Minjung Kim ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US10025275B2

公开(公告)日：2018-07-17

申请号：US15045690

申请日：2016-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunseok Kim ,  Younghoon Kwak ,  Dongkyu Kim ,  Sang-Hyen Park ,  Seungyun Lee

IPC: G04G21/08 ,  G09G3/36 ,  G06F1/32 ,  G04G9/00 ,  G04R20/26 ,  G04C17/00 ,  G04G11/00 ,  G04G21/02 ,  G04G21/04

Abstract: An apparatus and a method for displaying information are provided. The method includes, in a standby mode, maintaining a display in a transparent state, the display covering a clock module including hands of a clock, in response to a display event, adjusting transparency of a display area on the display, and displaying information corresponding to the display event on the display area.

公开(公告)号：US12237256B2

公开(公告)日：2025-02-25

申请号：US18183062

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Keung Beum Kim ,  Dongkyu Kim ,  Minjung Kim ,  Seokhyun Lee

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US12087744B2

公开(公告)日：2024-09-10

申请号：US18125170

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/3511

Abstract: A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

公开(公告)号：US11804427B2

公开(公告)日：2023-10-31

申请号：US17177305

申请日：2021-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Seokhyun Lee ,  Kyoung Lim Suk ,  Jaegwon Jang ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225

Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

公开(公告)号：US11605584B2

公开(公告)日：2023-03-14

申请号：US17329256

申请日：2021-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim Suk ,  Keung Beum Kim ,  Dongkyu Kim ,  Minjung Kim ,  Seokhyun Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

公开(公告)号：US20220302002A1

公开(公告)日：2022-09-22

申请号：US17498893

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu Kim ,  Minjung Kim ,  Kyounglim Suk ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/29

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.