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    Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts
    13.
    发明授权
    Semiconductor memory devices having vertical pillars that are electrically connected to lower contacts 有权

    公开(公告)号：US10043822B2

    公开(公告)日：2018-08-07

    申请号：US15706861

    申请日：2017-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： TaeHee Lee ,  Kyoung-Hoon Kim ,  Hongsoo Kim

    IPC: H01L29/792 ,  H01L27/11582

    Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

    Vertical memory devices
    16.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11456335B2

    公开(公告)日：2022-09-27

    申请号：US17031037

    申请日：2020-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongho Lim ,  Hoosung Cho ,  Hongsoo Kim

    IPC: H01L27/24 ,  H01L27/115 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/112 ,  H01L23/48

    Abstract: A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.

    VARIABLE RESISTANCE MEMORY DEVICES
    17.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES 有权

    公开(公告)号：US20220130430A1

    公开(公告)日：2022-04-28

    申请号：US17335520

    申请日：2021-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Boram Im ,  Hongsoo Kim ,  Jongkook Park ,  Hose Choi ,  Hyunju Sung

    IPC: G11C5/06 ,  G11C13/00

    Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

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