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    Coordinated in-module RAS features for synchronous DDR compatible memory
    11.
    发明授权
    Coordinated in-module RAS features for synchronous DDR compatible memory 有权

    公开(公告)号：US11294571B2

    公开(公告)日：2022-04-05

    申请号：US16819032

    申请日：2020-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

    IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C5/04 ,  G11C11/406 ,  G11C29/04

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    Coordinated in-module RAS features for synchronous DDR compatible memory
    12.
    发明授权
    Coordinated in-module RAS features for synchronous DDR compatible memory 有权

    公开(公告)号：US10592114B2

    公开(公告)日：2020-03-17

    申请号：US15213386

    申请日：2016-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng ,  Sun Young Lim ,  Indong Kim ,  Jangseok Choi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04 ,  G11C11/406 ,  G11C5/04

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    ADAPTIVE MECHANISM FOR SYNCHRONIZED OR ASYNCHRONIZED MEMORY DEVICES
    19.
    发明申请
    ADAPTIVE MECHANISM FOR SYNCHRONIZED OR ASYNCHRONIZED MEMORY DEVICES 有权

    公开(公告)号：US20170255398A1

    公开(公告)日：2017-09-07

    申请号：US15174761

    申请日：2016-06-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Benjamin Lim ,  Indong Kim

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0632 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/068 ,  G06F3/0685

    Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

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