公开(公告)号：US12079147B2

公开(公告)日：2024-09-03

申请号：US18170949

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-joo Jung ,  Jang-woo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm

IPC: G06F12/08 ,  G06F1/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/0882 ,  G06F13/16 ,  G06F18/214

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F11/0757 ,  G06F11/3037 ,  G06F12/0882 ,  G06F18/2148

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

公开(公告)号：USRE49206E1

公开(公告)日：2022-09-06

申请号：US16692483

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Woon Kang ,  Jeong-don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: H03K19/0175 ,  G11C7/00 ,  H03H7/38 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/02 ,  H03K19/00 ,  G11C16/04 ,  G11C29/50

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

公开(公告)号：US20200379862A1

公开(公告)日：2020-12-03

申请号：US16999168

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-joo Jung ,  Jang-woo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm

IPC: G06F11/30 ,  G06F11/07 ,  G06F12/0882 ,  G06F13/16 ,  G06F1/10 ,  G06K9/62

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

公开(公告)号：US10824575B2

公开(公告)日：2020-11-03

申请号：US15979625

申请日：2018-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-woo Lee ,  Jeong-don Ihm ,  Byung-hoon Jeong

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/22 ,  G11C29/02 ,  G11C7/10 ,  G11C5/04

Abstract: A memory system and a buffer device include a structure for performing training operations for a plurality of memory devices to ensure data reliability. A memory controller is configured to control a memory operation for a plurality of memory devices. A memory module includes the plurality of memory devices and a buffer device connected between the memory devices and the memory controller. Training operations for the memory devices to be performed by the buffer device including a training block with a signal delay circuit, and the memory controller performs the training operations by controlling the training block.

公开(公告)号：US10600454B2

公开(公告)日：2020-03-24

申请号：US15975266

申请日：2018-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-su Jang ,  Man-jae Yang ,  Jeong-don Ihm ,  Go-eun Jung ,  Byung-hoon Jeong ,  Young-don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10132865B2

公开(公告)日：2018-11-20

申请号：US15170940

申请日：2016-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-kyoo Lee ,  Jeong-don Ihm ,  Byung-hoon Jeong ,  Dae-woon Kang ,  Tae-sung Lee ,  Sang-lok Kim

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/317

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).