公开(公告)号：US11432418B2

公开(公告)日：2022-08-30

申请号：US16742191

申请日：2020-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinho Yoon ,  Jonghyuck Lee ,  Taeik Kim ,  Haeyeon Kim ,  Dongjun Oh ,  Soonho Hwang

IPC: H05K5/02 ,  H01Q1/22 ,  H05K5/00 ,  H01Q1/36 ,  H01Q1/50 ,  H05K1/18 ,  H05K5/03 ,  H05K7/14

Abstract: An electronic device is provided. The electronic device includes a first housing structure including a conductive first side member, a second housing structure including a conductive second side member, a hinge structure rotatably connecting the first housing structure and the second housing structure, and a printed circuit board. The first side member or the second side member may include a first side face, a second side face, a third side face, a fourth side face, a first slit formed in the fourth side face, and a second slit formed in any one of the first side face, the second side face, and the third side face. At least a part of the second side face or the third side face between the first slit and the second slit may be made of a conductive material and electrically connected to the printed circuit board as a radiating conductor.

公开(公告)号：US10193562B2

公开(公告)日：2019-01-29

申请号：US15802601

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangyeop Choo ,  Wonsik Yu ,  Wooseok Kim ,  Jihyun Kim ,  Taeik Kim ,  Hyunik Kim

IPC: H03D3/24 ,  H03L7/107 ,  H03L7/099 ,  H03L7/199 ,  H03L7/18 ,  H03L7/087 ,  H03L7/091

Abstract: A digital phase locked loop circuit includes a phase frequency detector, a bandwidth calibrator, a digital loop filter, and a digital controlled oscillator. The phase frequency detector generates a first detection value and a second detection value of which each is associated with order between a phase of a reference signal and a phase of a fed-back signal. The bandwidth calibrator amplifies a signal level of the second detection value by a gain value to generate an amplified detection value, and adjusts the gain value based on the first detection value. The digital loop filter generates a digital code based on the amplified detection value. The digital controlled oscillator generates an output signal having a frequency which corresponds to the digital code. The fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.

公开(公告)号：US20160156362A1

公开(公告)日：2016-06-02

申请号：US14817727

申请日：2015-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-JIN KIM ,  Jihyun Kim ,  Taeik Kim

IPC: H03L7/189 ,  G04F10/00

CPC classification number: H03L7/189 ,  G04F10/005 ,  H03L7/085 ,  H03L7/18

Abstract: Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period.

Abstract translation: 提供了一个时间 - 数字转换器。 时间数字转换器包括若干延迟电路，被配置为对延迟电路的输出进行计数的加法器和被配置为从加法器输出的结果中截断预定数量的LSB的最低有效位（LSB）截断电路。 时间数字转换器被配置为在具有预定周期的时钟的一个周期内确定起始信号和停止信号之间的时间间隔。

公开(公告)号：US11758673B2

公开(公告)日：2023-09-12

申请号：US17871324

申请日：2022-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinho Yoon ,  Jonghyuck Lee ,  Taeik Kim ,  Haeyeon Kim ,  Dongjun Oh ,  Soonho Hwang

IPC: H05K5/02 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q1/50 ,  H05K1/18 ,  H05K5/00 ,  H05K5/03 ,  H05K7/14 ,  H04M1/02

CPC classification number: H05K5/0226 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q1/50 ,  H05K1/181 ,  H05K5/0017 ,  H05K5/03 ,  H05K7/1427 ,  H04M1/0268 ,  H05K2201/10098

Abstract: An electronic device is provided. The electronic device includes a first housing structure including a conductive first side member, a second housing structure including a conductive second side member, a hinge structure rotatably connecting the first housing structure and the second housing structure, and a printed circuit board. The first side member or the second side member may include a first side face, a second side face, a third side face, a fourth side face, a first slit formed in the fourth side face, and a second slit formed in any one of the first side face, the second side face, and the third side face. At least a part of the second side face or the third side face between the first slit and the second slit may be made of a conductive material and electrically connected to the printed circuit board as a radiating conductor.

公开(公告)号：US20220239284A1

公开(公告)日：2022-07-28

申请号：US17466006

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsik Yu ,  Wooseok Kim ,  Taeik Kim ,  Chanyoung Jeong

IPC: H03K3/011 ,  H03K3/037 ,  G06F1/08 ,  G06F1/12

Abstract: A clock generation circuit includes a temperature compensation circuit and an oscillator. The temperature compensation circuit is configured to generate a temperature-compensated frequency selection code that varies depending on an operation temperature based on a difference between the operation temperature and a reference temperature and based on a temperature-independent frequency selection code that is fixed regardless of the operation temperature. The oscillator is configured to generate a clock signal that has an operation frequency that is based on the temperature-compensated frequency selection code, such that the operation frequency is uniform regardless of the operation temperature. Effects of the operation temperature may be reduced by generating the temperature-compensated frequency selection code that reflects the temperature characteristic of the oscillator using the output value of the temperature sensor and by controlling the oscillator using the temperature-compensated frequency selection code.

公开(公告)号：US10256826B2

公开(公告)日：2019-04-09

申请号：US15229499

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Kim ,  Jihyun Kim ,  Taeik Kim

IPC: H04B1/69 ,  B32B3/18 ,  H03L7/08 ,  G06F1/08 ,  H03B1/00 ,  H03D3/24 ,  B32B3/26 ,  H03L7/00 ,  G06F1/10 ,  H02M3/07 ,  H03K5/26 ,  H03L7/093 ,  H03L7/099

Abstract: A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.

公开(公告)号：US09490831B2

公开(公告)日：2016-11-08

申请号：US14817727

申请日：2015-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Jin Kim ,  Jihyun Kim ,  Taeik Kim

IPC: H03L7/06 ,  H03L7/189 ,  G04F10/00

CPC classification number: H03L7/189 ,  G04F10/005 ,  H03L7/085 ,  H03L7/18

Abstract: Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period.

Abstract translation: 提供了一个时间 - 数字转换器。 时间数字转换器包括若干延迟电路，被配置为对延迟电路的输出进行计数的加法器和被配置为从加法器输出的结果中截断预定数量的LSB的最低有效位（LSB）截断电路。 时间数字转换器被配置为在具有预定周期的时钟的一个周期内确定起始信号和停止信号之间的时间间隔。