公开(公告)号：US10593393B2

公开(公告)日：2020-03-17

申请号：US16502943

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JoongShik Shin ,  Byoungil Lee ,  Hyunmog Park ,  Euntaek Jung

IPC: H01L29/76 ,  G11C11/408 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  G11C8/08 ,  G11C8/12 ,  G11C11/06 ,  H01L21/8239 ,  H01L23/528

Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

公开(公告)号：US20230269941A1

公开(公告)日：2023-08-24

申请号：US18095576

申请日：2023-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong Lee ,  Yukio Hayakawa ,  Taeyoung Kim ,  Hyunmog Park ,  Siyeon Cho

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  G11C16/14

CPC classification number: H10B43/27 ,  H10B43/35 ,  H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  G11C16/14

Abstract: A semiconductor device includes a source structure, gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to an upper surface of the source structure, and a channel structure extending through the gate electrodes in the first direction, and including a dielectric layer, a charge storage layer, a tunneling layer, a channel layer, and a buried semiconductor layer. The dielectric layer is between the gate electrodes and the charge storage layer. The tunneling layer is between charge storage layer and the channel layer. The channel layer is between the tunneling layer and the buried semiconductor layer. An outer surface of a lower portion of the channel layer is in contact with the source structure, and the dielectric layer includes a ferroelectric material, the channel layer includes an oxide semiconductor material, and the buried semiconductor layer includes silicon (Si).

公开(公告)号：US11482267B2

公开(公告)日：2022-10-25

申请号：US17330828

申请日：2021-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US11062751B2

公开(公告)日：2021-07-13

申请号：US16704320

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C11/22 ,  G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US10998330B2

公开(公告)日：2021-05-04

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmog Park ,  Daewoong Kang ,  Chadong Yeo ,  Jaehoon Jang ,  Joongshik Shin

IPC: H01L29/04 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L29/49 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

公开(公告)号：US10373673B2

公开(公告)日：2019-08-06

申请号：US15614714

申请日：2017-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JoongShik Shin ,  Byoungil Lee ,  Hyunmog Park ,  Euntaek Jung

IPC: H01L29/76 ,  G11C11/408 ,  G11C8/08 ,  G11C8/12 ,  G11C11/06 ,  H01L21/8239 ,  H01L23/528 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.

公开(公告)号：US12029048B2

公开(公告)日：2024-07-02

申请号：US17526262

申请日：2021-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmog Park ,  Jungyu Lee ,  Daehwan Kang ,  Sungho Eun

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  G11C13/0023 ,  H10N70/011 ,  H10N70/882

Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.

公开(公告)号：US11508851B2

公开(公告)日：2022-11-22

申请号：US17004427

申请日：2020-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Hyunmog Park ,  Minwoo Song ,  Woobin Song ,  Hyunsil Oh ,  Minsu Lee

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/24

Abstract: A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

公开(公告)号：US11488956B2

公开(公告)日：2022-11-01

申请号：US17313570

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomyong Hwang ,  Min Hee Cho ,  Hei Seung Kim ,  Mirco Cantoro ,  Hyunmog Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/10 ,  H01L27/108 ,  G11C11/402

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

公开(公告)号：US11342330B2

公开(公告)日：2022-05-24

申请号：US17172124

申请日：2021-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Hyunmog Park ,  Woo Bin Song ,  Minsu Lee ,  Wonsok Lee

IPC: H01L27/108

Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.