公开(公告)号：US09747992B1

公开(公告)日：2017-08-29

申请号：US15172671

申请日：2016-06-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C8/08 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427

Abstract: A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal.

公开(公告)号：US20160358662A1

公开(公告)日：2016-12-08

申请号：US15208843

申请日：2016-07-13

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C11/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459

Abstract: Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word lines, word line voltages are ramped down, but no later than the ramping down of the voltages of the select gates. The timing of the ramp down of the selected word line depends on whether it is among the predefined subset or the remaining subset. The predefined subset can include a number of adjacent or non-adjacent word lines.

Abstract translation: 通过控制字线的幅度和时序并在感测操作结束时选择栅极斜坡下降电压，在3D存储器件中减少了由于热电子注入引起的读取干扰。 在示例性读取操作中，字线的预定义子集包括源侧和漏极字线。 对于字线的预定义子集，字线电压在选择门的电压下降之前下降。 随后，对于字线的剩余子集，字线电压下降，但不迟于选择栅极的电压的斜降。 所选字线的斜坡下降的时间取决于它是否在预定义的子集或剩余子集之间。 预定义子集可以包括多个相邻或不相邻的字线。

公开(公告)号：US10685723B1

公开(公告)日：2020-06-16

申请号：US16227668

申请日：2018-12-20

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Wei Zhao ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/32 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. A discharge period is set based on a position of the selected word line in a stack or block of memory cells. The discharge period is longer when the selected word line is in the lower tier than in the upper tier. Additionally, the discharge period is longer when the selected word line is at a top of the lower tier than at a bottom of the lower tier. Other options to increase the discharge include increasing a ramp up rate and a peak level of the word line voltages during the discharge period as a function of the position of the selected word line.

公开(公告)号：US10665306B1

公开(公告)日：2020-05-26

申请号：US16377421

申请日：2019-04-08

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Henry Chin

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C7/10 ,  G11C16/26 ,  G11C7/04 ,  G11C16/16

Abstract: Techniques are disclosed for reducing an injection type of program disturb in a memory device. In one aspect, a discharge operation is performed at the start of a program loop. This operation discharges residue electrons from the channel region on the source side of the selected word line, WLn, to the channel region on the drain side of WLn. As a result, in a subsequent channel pre-charge operation, the residue electrons can be more easily removed from the channel. The discharge operation involves applying a voltage pulse to WLn and a first set of drain-side word lines which is adjacent to WLn. The remaining unselected word lines may be held at ground during the voltage pulse.

公开(公告)号：US10665299B1

公开(公告)日：2020-05-26

申请号：US16385430

申请日：2019-04-16

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Hong-Yan Chen

IPC: G11C16/04 ,  G11C16/00 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556 ,  G11C11/56

Abstract: Techniques are disclosed for reducing an injection type of read disturb in a memory device. During a program loop, when NAND strings in a selected sub-block are programmed, a pre-verify voltage pulse is applied to a selected word line and to a select gate transistor to discharge the drain-side channel in NAND strings of unselected sub-blocks. The duration of the pulse can vary for the different unselected sub-blocks and can be based on a sub-block programming order. In another aspect, the duration is higher for initial program loops in a program operation, when lower data states are being verified, and then decreases to a lower level for subsequent program loops when higher data states are being verified.

公开(公告)号：US20190147962A1

公开(公告)日：2019-05-16

申请号：US15814769

申请日：2017-11-16

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/26 ,  H01L27/11529

Abstract: A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.

公开(公告)号：US20190147955A1

公开(公告)日：2019-05-16

申请号：US15814772

申请日：2017-11-16

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/32 ,  G11C16/30

Abstract: A memory device and associated techniques for reducing hot electron injection type of disturbs of memory cells. In one approach, after a pre-charge operation, voltages of a first group of adjacent word lines comprising a selected word line (WLn) and one or more drain-side word lines of WLn are increased after voltages of remaining word lines are increased. In another approach, after the pre-charge operation, voltages of the first group of adjacent word lines are increased in steps while voltages of remaining word lines are continuously increased. In another approach, voltages of the first group of adjacent word lines are increased from a negative voltage while voltages of remaining word lines are increased from 0 V. In another aspect, the disturb countermeasures can be implemented according to the position of WLn in a multi-tier stack.

公开(公告)号：US10283202B1

公开(公告)日：2019-05-07

申请号：US15814772

申请日：2017-11-16

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: A memory device and associated techniques for reducing hot electron injection type of disturbs of memory cells. In one approach, after a pre-charge operation, voltages of a first group of adjacent word lines comprising a selected word line (WLn) and one or more drain-side word lines of WLn are increased after voltages of remaining word lines are increased. In another approach, after the pre-charge operation, voltages of the first group of adjacent word lines are increased in steps while voltages of remaining word lines are continuously increased. In another approach, voltages of the first group of adjacent word lines are increased from a negative voltage while voltages of remaining word lines are increased from 0 V. In another aspect, the disturb countermeasures can be implemented according to the position of WLn in a multi-tier stack.

公开(公告)号：US10217518B1

公开(公告)日：2019-02-26

申请号：US15678683

申请日：2017-08-16

Applicant: SanDisk Technologies LLC

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28 ,  G11C16/04 ,  G11C16/30

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. The drain-end select gate transistors of unselected sub-blocks are made temporarily conductive for a time period during the ramp up of the unselected word line voltages to reduce the amount of capacitive coupling up of the respective memory string channel. This reduces a channel gradient which can exist in the memory string channels, thereby also reducing the read disturb. Further, the time period is greater when the selected word line is in a source-end or midrange subset of the word lines than when the selected word line is in a drain-end subset of the word lines. Another option involves omitting the injection disturb countermeasure, or providing a less severe injection disturb countermeasure, when the unselected sub-blocks are unprogrammed.

公开(公告)号：US10121552B1

公开(公告)日：2018-11-06

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/32 ,  G11C16/08

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.