公开(公告)号：US20180315794A1

公开(公告)日：2018-11-01

申请号：US15498255

申请日：2017-04-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepak Kamalanathan ,  Sebastian J. M. Wicklein ,  Juan Saenz ,  Ming-Che Wu

IPC: H01L27/24 ,  H01L45/00

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The nonvolatile memory material includes a semiconductor material layer, and a conductive oxide material layer including a first conductive oxide material layer portion and a second conductive oxide material layer portion. The method also includes forming a barrier material layer between the first conductive oxide material layer portion and the second conductive oxide material layer portion.

公开(公告)号：US20180159033A1

公开(公告)日：2018-06-07

申请号：US15890296

申请日：2018-02-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ming-Che Wu ,  Tanmay Kumar

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  G11C11/56

CPC classification number: H01L45/146 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.

公开(公告)号：US09806256B1

公开(公告)日：2017-10-31

申请号：US15299919

申请日：2016-10-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ming-Che Wu ,  Chuanbin Pan ,  Guangle Zhou ,  Tanmay Kumar

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/124 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/51 ,  G11C2213/52 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1675

Abstract: A resistive memory device includes a first electrode, a sidewall spacer electrode located on a sidewall of a dielectric material contacting the first electrode, a resistive memory cell containing a resistive memory material and contacting the sidewall spacer electrode, and a second electrode containing the resistive memory cell.