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公开(公告)号：US10340449B2
公开(公告)日：2019-07-02
申请号：US15611029
申请日：2017-06-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Alvaro Padilla , Tanmay Kumar
Abstract: A resistive memory device, such as a BMC ReRAM device, includes at least one resistive memory element which contains a carbon barrier material portion and a resistive memory material portion that is disposed between a first electrode and a second electrode.
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公开(公告)号：US10283708B2
公开(公告)日：2019-05-07
申请号：US15452373
申请日：2017-03-07
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
IPC: H01L45/00 , H01L27/24 , H01L27/105 , G11C13/00 , H01L27/115
Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US20180261766A1
公开(公告)日：2018-09-13
申请号：US15452373
申请日：2017-03-07
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Deepak Kamalanathan , Juan Saenz , Tanmay Kumar
CPC classification number: H01L45/1608 , G11C7/18 , G11C8/14 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/16
Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.
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公开(公告)号：US10109680B1
公开(公告)日：2018-10-23
申请号：US15622100
申请日：2017-06-14
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Sebastian J. M. Wicklein , Juan P. Saenz , Srikanth Ranganathan , Ming-Che Wu , Tanmay Kumar
Abstract: A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.
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公开(公告)号：US09923140B2
公开(公告)日：2018-03-20
申请号：US15269999
申请日：2016-09-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L45/146 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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Patent Agency Ranking
公开(公告)号：US20170309819A1
公开(公告)日：2017-10-26
申请号：US15269999
申请日：2016-09-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L45/146 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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公开(公告)号：US10943952B2
公开(公告)日：2021-03-09
申请号：US16435843
申请日：2019-06-10
Applicant: SanDisk Technologies LLC
Inventor： Federico Nardi , Ming-Che Wu , Tim Minvielle , Zhaoqiang Bai
Abstract: The switching device includes three terminals including an inner surface, an oxide layer on the inner surface of the third terminal, and a chalcogenide pillar extending through the oxide layer and the third terminal, the pillar being in electrical communication with the first terminal and the second terminal, wherein the voltage difference between the first terminal and the second terminal changes the channel from a first state to a second state when a threshold voltage between the first terminal and the second terminal is exceeded, the threshold voltage being dependent on temperature. The third terminal is resistive and receives a control signal to apply heat to the pillar and modulate the threshold voltage. The switching device can be used to select the memory stack through the bitline and provide a nearly limitless current based on the threshold switching conduction providing avalanche current conduction through the switching device.
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公开(公告)号：US20180247975A1
公开(公告)日：2018-08-30
申请号：US15441284
申请日：2017-02-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Juan Saenz , Deepak Kamalanathan , Guangle Zhou , Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L27/249 , H01L27/2454 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/1683
Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
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公开(公告)号：US10283567B2
公开(公告)日：2019-05-07
申请号：US15441284
申请日：2017-02-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Juan Saenz , Deepak Kamalanathan , Guangle Zhou , Ming-Che Wu , Tanmay Kumar
Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.
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公开(公告)号：US10276792B2
公开(公告)日：2019-04-30
申请号：US15890296
申请日：2018-02-06
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
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