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公开(公告)号：US20210407596A1
公开(公告)日：2021-12-30
申请号：US16912917
申请日：2020-06-26
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng
Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.
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公开(公告)号：US11211127B1
公开(公告)日：2021-12-28
申请号：US16912917
申请日：2020-06-26
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Hua-Ling Hsu , Huai-Yuan Tseng
IPC: G11C11/56 , G11C16/04 , G11C16/10 , G11C16/24 , G11C16/32 , H01L27/11582 , H01L27/11519 , H01L27/11565 , H01L27/11556
Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.
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公开(公告)号：US11972801B2
公开(公告)日：2024-04-30
申请号：US17665824
申请日：2022-02-07
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Yu-Chung Lien , Sarath Puthenthermadam , Sujjatul Islam
Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.
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公开(公告)号：US11875842B2
公开(公告)日：2024-01-16
申请号：US17522414
申请日：2021-11-09
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Deepanshu Dutta , Tai-Yuan Tseng
IPC: G11C7/12 , G11C11/4096 , G11C11/408 , G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4096 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087
Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.
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15.发明授权公开(公告)号：US11790992B2
公开(公告)日：2023-10-17
申请号：US17359989
申请日：2021-06-28
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-yuan Tseng
IPC: G11C16/26 , G11C16/06 , G11C16/10 , G11C16/04 , G11C16/08 , G11C11/56 , G11C16/34 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
CPC classification number: G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.
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Patent Agency Ranking
公开(公告)号：US20230290403A1
公开(公告)日：2023-09-14
申请号：US17690332
申请日：2022-03-09
Applicant: SanDisk Technologies LLC
Inventor： Jiahui Yuan , Kai Kirk , Yu-Chung Lien
IPC: G11C11/4096 , G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4096 , G11C11/4074 , G11C11/4076
Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.
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公开(公告)号：US20230274785A1
公开(公告)日：2023-08-31
申请号：US17682280
申请日：2022-02-28
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Yu-Chung Lien , Ravi Kumar , Xue Pitner
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/24 , G11C16/14 , G11C16/26
Abstract: A non-volatile semiconductor memory device comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.
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公开(公告)号：US11600343B2
公开(公告)日：2023-03-07
申请号：US17329390
申请日：2021-05-25
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Tomer Eliash , Huai-Yuan Tseng
IPC: G11C16/04 , G11C16/34 , G11C16/26 , G11C16/08 , H01L27/11582 , H01L27/11565 , G11C11/56 , H01L25/065
Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.
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19.发明申请公开(公告)号：US20220415399A1
公开(公告)日：2022-12-29
申请号：US17359989
申请日：2021-06-28
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Huai-yuan Tseng
Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.
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公开(公告)号：US20220415398A1
公开(公告)日：2022-12-29
申请号：US17360677
申请日：2021-06-28
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Jiahui Yuan , Deepanshu Dutta
Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.
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