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11.发明公开公开(公告)号：US20230352518A1
公开(公告)日：2023-11-02
申请号：US18346430
申请日：2023-07-03
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Rick Carlton JEROME , Gordon M. GRIVNA , Kevin Alexander STEWART , David T. PRICE , Jeffrey Peter GAMBINO
Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.
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公开(公告)号：US20230261015A1
公开(公告)日：2023-08-17
申请号：US18305959
申请日：2023-04-24
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Jeffrey Peter GAMBINO , Kyle THOMAS , David T. PRICE , Rusty WINZENREAD , Bruce GREENWOOD
IPC: H01L27/146
CPC classification number: H01L27/14618 , H01L27/14636 , H01L27/14634
Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.
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公开(公告)号：US20220367534A1
公开(公告)日：2022-11-17
申请号：US17302836
申请日：2021-05-13
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Jeffrey Peter GAMBINO , David T. PRICE , Marc Allen SULFRIDGE , Richard MAURITZSON , Michael Gerard KEYES , Ryan RETTMANN , Kevin MCSTAY
IPC: H01L27/146
Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.
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公开(公告)号：US20250125284A1
公开(公告)日：2025-04-17
申请号：US18488628
申请日：2023-10-17
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Jeffrey Peter GAMBINO , David T. PRICE , Marc Allen SULFRIDGE , Richard MAURITZSON , James Joseph STEFFES
IPC: H01L23/60 , H01L23/00 , H01L27/146
Abstract: A semiconductor device may include a first chip with a first wafer and a first dielectric layer, and a second chip that includes a second wafer and a second dielectric layer, the second chip having a backside surface and a frontside surface opposed to the backside surface and bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. The semiconductor device may include a die seal layer on the backside surface having a die seal ground contact in contact with the second wafer, and an electrostatic discharge path that includes the die seal layer, the die seal ground contact, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line.
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公开(公告)号：US20240387581A1
公开(公告)日：2024-11-21
申请号：US18789169
申请日：2024-07-30
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Manuel H. INNOCENT , Tomas GEURTS , David T. PRICE
IPC: H01L27/146
Abstract: Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.
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Patent Agency Ranking
公开(公告)号：US20240371905A1
公开(公告)日：2024-11-07
申请号：US18309933
申请日：2023-05-01
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Swarnal BORTHAKUR , Marc Allen SULFRIDGE , Jeffrey Peter GAMBINO , Vladimir KOROBOV , Richard MAURITZSON , David T. PRICE
IPC: H01L27/146 , H01L23/58
Abstract: A semiconductor device may include a first chip that includes a first wafer and a first dielectric layer disposed thereon. The semiconductor device may include a second chip that includes a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. An opening through the backside surface of the second chip may extend into the second dielectric layer, and a bond pad may be disposed within the second dielectric layer between the second wafer and the bond line.
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公开(公告)号：US20240321924A1
公开(公告)日：2024-09-26
申请号：US18673521
申请日：2024-05-24
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Jeffrey Peter GAMBINO , David T. PRICE , Marc Allen SULFRIDGE , Richard MAURITZSON , Michael Gerard KEYES , Ryan RETTMANN , Kevin MCSTAY
IPC: H01L27/146
CPC classification number: H01L27/1463 , H01L27/14603 , H01L27/14623 , H01L27/1464
Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.
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公开(公告)号：US20220003800A1
公开(公告)日：2022-01-06
申请号：US17011027
申请日：2020-09-03
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Kevin Alexander STEWART , Martin KEJHAR , Radim MLCOUSEK , Arash ELHAMI KHORASANI , David T. PRICE , Mark GRISWOLD
Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.
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公开(公告)号：US20190043903A1
公开(公告)日：2019-02-07
申请号：US16116634
申请日：2018-08-29
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Jeffrey Peter GAMBINO , Angel RODRIGUEZ , David T. PRICE , Jeffery Allen NEULS , Kenneth Andrew BATES , Rick MAURITZSON
IPC: H01L27/146 , H01L27/06
CPC classification number: H01L27/14609 , H01L27/0617 , H01L27/1463 , H01L27/14634 , H01L27/14636
Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.
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公开(公告)号：US20180219038A1
公开(公告)日：2018-08-02
申请号：US15421505
申请日：2017-02-01
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Jeffrey Peter GAMBINO , Kyle THOMAS , David T. PRICE , Rusty WINZENREAD , Bruce GREENWOOD
IPC: H01L27/146
CPC classification number: H01L27/14618 , H01L27/14634 , H01L27/14636
Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.
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