公开(公告)号：US20220230885A1

公开(公告)日：2022-07-21

申请号：US17658071

申请日：2022-04-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of a die included in each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.

公开(公告)号：US20220157756A1

公开(公告)日：2022-05-19

申请号：US17649943

申请日：2022-02-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Sw WANG ,  CH CHEW ,  Eiji KUROSE ,  How Kiat LIEW

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

公开(公告)号：US20210159210A1

公开(公告)日：2021-05-27

申请号：US17163674

申请日：2021-02-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Eiji KUROSE

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/285

Abstract: Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.

公开(公告)号：US20200286735A1

公开(公告)日：2020-09-10

申请号：US16879251

申请日：2020-05-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

公开(公告)号：US20170352582A1

公开(公告)日：2017-12-07

申请号：US15175191

申请日：2016-06-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Eiji KUROSE

IPC: H01L21/768 ,  H01L21/48

Abstract: A process of forming an electronic device including providing a substrate having a first surface and a second surface opposite the first surface; etching the substrate along the first surface to define a trench; forming a via within the trench; applying a tape including an adhesive to the first surface, wherein the adhesive of the tape is spaced apart from the first surface by a distance; and operating on the second surface of the substrate.

公开(公告)号：US20240379603A1

公开(公告)日：2024-11-14

申请号：US18313425

申请日：2023-05-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Eiji KUROSE

IPC: H01L23/00

Abstract: A semiconductor device component includes a contact pad disposed on a surface of a semiconductor substrate, a seed metal layer disposed on the contact pad, and an interconnect disposed on the seed metal layer. The seed metal layer has a width that is greater than the width of the interconnect with a footer portion of the seed metal layer extending outside the width of the interconnect. The semiconductor device component further includes an etch-resistant protective structure disposed on surfaces of the interconnect and the footer portion of the seed metal layer extending outside the width of the interconnect.

公开(公告)号：US20240332025A1

公开(公告)日：2024-10-03

申请号：US18742204

申请日：2024-06-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31

CPC classification number: H01L21/302 ,  H01L21/48 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L24/04 ,  H01L24/26 ,  H01L2224/94

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20220384204A1

公开(公告)日：2022-12-01

申请号：US17808338

申请日：2022-06-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Michael J. SEDDON ,  Yusheng LIN ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/3065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

公开(公告)号：US20220351977A1

公开(公告)日：2022-11-03

申请号：US17813348

申请日：2022-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20220301876A1

公开(公告)日：2022-09-22

申请号：US17806144

申请日：2022-06-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Eiji KUROSE ,  Chee Hiong CHEW ,  Soon Wei WANG

IPC: H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/31

Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.